Abstract: A method of forming a power semiconductor device includes providing an epi layer over a substrate; forming a well at an upper portion of the epi layer; forming a pillar below the well and spaced apart from the well to define a Schottky contact region; etching a trench into the epi layer, the trench having a sidewall and a base, a portion of the sidewall of the trench corresponding to the Schottky contact region; forming a metal contact layer over the sidewall and the base of the trench, the metal contact layer forming a Schottky interface with the epi layer at the Schottky contact region; and forming a gate electrode and first and second electrodes.

Abstract: An electronic device can include a die that has an active region and a termination region. Pillars within an active region near the termination region can help reduce an electrical field near a boundary of the active and termination regions adjacent to a primary surface of a substrate. In an embodiment, the reduced electrical field may be achieved by having reduced net charge within pillars of the active region near the termination region, as opposed to pillars near the center of the active region. In another embodiment, the reduced electrical field can be achieved by partially doping pillars within the active region that are closer to the termination region or by at least partly counter doping such pillars.

Abstract: An electronic device can include a semiconductor layer having a primary surface, a drift region adjacent to the primary surface, a drain region adjacent to the drift region and extending deeper into the semiconductor layer as compared to the drift region, a resurf region spaced apart from the primary surface, an insulating layer overlying the drain region, and a contact extending through the insulating layer to the drain region. In an embodiment, the drain region can include a sinker region that allows a bulk breakdown to the resurf region to occur during an overvoltage event where the bulk breakdown occurs outside of the drift region, and in a particular embodiment, away from a shallow trench isolation structure or other sensitive structure.

Abstract: A method of forming a power semiconductor device includes providing an epi layer over a substrate; forming a well at an upper portion of the epi layer; forming a pillar below the well and spaced apart from the well to define a Schottky contact region; etching a trench into the epi layer, the trench having a sidewall and a base, a portion of the sidewall of the trench corresponding to the Schottky contact region; forming a metal contact layer over the sidewall and the base of the trench, the metal contact layer forming a Schottky interface with the epi layer at the Schottky contact region; and forming a gate electrode and first and second electrodes.

Abstract: Systems and methods of the disclosed embodiments include a semiconductor device that includes an N-doped pillar with a gate structure configured to control a signal between a drain and a source in response to a gate voltage signal. The semiconductor device may also include a P-doped pillar with a capacitive structure. The capacitive structure capacitively couples the P-doped pillar to the gate structure to reduce ringing in the gate voltage signal.

Abstract: A power semiconductor device includes a semiconductor layer having a first conductivity type. A trench is defined within the semiconductor layer, the trench having an opening, a sidewall and a base. A pillar is provided below the trench and has a second conductivity type that is different than the first conductivity type. A metal layer is provided over the sidewall of the trench, the metal layer contacting the semiconductor layer at the sidewall of the trench to form a Schottky interface of a Schottky diode. A first electrode is provided over a first side of the semiconductor layer. A second electrode is provided over a second side of the semiconductor layer.

Abstract: A transistor device includes an n-doped pillar and a p-doped pillar forming a super-junction structure on a substrate. An isolation structure is disposed in a trench between the n-doped pillar and the p-doped pillar, and a source and a gate are disposed on the n-doped pillar. The isolation structure can include an air gap encapsulated in the trench by an oxide plug. The isolation structure can include an epi liner disposed on surfaces of the n-doped pillar and the p-doped pillar.

Abstract: An electronic device can include a transistor having a drain region, a source region, a dielectric layer, and a gate electrode. The dielectric layer can have a first portion and a second portion, wherein the first portion is relatively thicker and closer to the drain region; the second portion is relatively thinner and closer to the source region. The gate electrode of the transistor can overlie the first and second portions of the dielectric layer. In another aspect, an electronic device can be formed using two different dielectric layers having different thicknesses. A gate electrode within the electronic device can be formed over portions of the two different dielectric layers. The process can eliminate masking and doping steps that may be otherwise used to keep the drain dopant concentration closer to the concentration as originally formed.

Abstract: A power semiconductor device includes a semiconductor layer having a first conductivity type. A trench is defined within the semiconductor layer, the trench having an opening, a sidewall and a base. A pillar is provided below the trench and has a second conductivity type that is different than the first conductivity type. A metal layer is provided over the sidewall of the trench, the metal layer contacting the semiconductor layer at the sidewall of the trench to form a Schottky interface of a Schottky diode. A first electrode is provided over a first side of the semiconductor layer. A second electrode is provided over a second side of the semiconductor layer.

Abstract: An electronic device can include a transistor structure. In an embodiment, the transistor structure can include a channel region and a drift structure including different semiconductor base materials. In another embodiment, the transistor structure can include a source region and a drain structure including a first region, wherein the source region and the first region include different semiconductor base materials and have the same conductivity type. In another aspect, a process of forming an electronic device can include forming a semiconductor layer; forming a body region; patterning the body region and the semiconductor layer to define a trench having a sidewall; forming a first region of a drain structure along the sidewall of the trench, wherein the first region and body region include different semiconductor base materials and different conductivity types.

Abstract: An electronic device can include a semiconductor layer having a primary surface, a drift region adjacent to the primary surface, a drain region adjacent to the drift region and extending deeper into the semiconductor layer as compared to the drift region, a resurf region spaced apart from the primary surface, an insulating layer overlying the drain region, and a contact extending through the insulating layer to the drain region. In an embodiment, the drain region can include a sinker region that allows a bulk breakdown to the resurf region to occur during an overvoltage event where the bulk breakdown occurs outside of the drift region, and in a particular embodiment, away from a shallow trench isolation structure or other sensitive structure.

Abstract: An electronic device can include a termination structure that includes a substrate, a semiconductor layer, and a first trench. The substrate includes a semiconductor material of a first conductivity type. The semiconductor layer has a second conductivity type opposite the first conductivity type and overlies the substrate and has a primary surface. The first trench extends through a majority of a thickness of the semiconductor layer. In an embodiment, a body extension region of the second conductivity type is adjacent to the primary surface and spaced apart from the first trench. In another embodiment, a doped region of the first conductivity type is adjacent to the primary surface and abuts the first trench. In a further embodiment, the termination structure can include a second trench extending through a majority of the thickness of the semiconductor layer and a doped region is spaced apart from the first and second trenches.

Abstract: An electronic device can include a transistor structure. In an embodiment, the transistor structure can include a channel region and a drift structure including different semiconductor base materials. In another embodiment, the transistor structure can include a source region and a drain structure including a first region, wherein the source region and the first region include different semiconductor base materials and have the same conductivity type. In another aspect, a process of forming an electronic device can include forming a semiconductor layer; forming a body region; patterning the body region and the semiconductor layer to define a trench having a sidewall; forming a first region of a drain structure along the sidewall of the trench, wherein the first region and body region include different semiconductor base materials and different conductivity types.

Abstract: An electronic device can include a semiconductor layer having a primary surface, a drift region adjacent to the primary surface, a drain region adjacent to the drift region and extending deeper into the semiconductor layer as compared to the drift region, a resurf region spaced apart from the primary surface, an insulating layer overlying the drain region, and a contact extending through the insulating layer to the drain region. In an embodiment, the drain region can include a sinker region that allows a bulk breakdown to the resurf region to occur during an overvoltage event where the bulk breakdown occurs outside of the drift region, and in a particular embodiment, away from a shallow trench isolation structure or other sensitive structure.

Abstract: An electronic device can include a termination structure that includes a substrate, a semiconductor layer, and a first trench. The substrate includes a semiconductor material of a first conductivity type. The semiconductor layer has a second conductivity type opposite the first conductivity type and overlies the substrate and has a primary surface. The first trench extends through a majority of a thickness of the semiconductor layer. In an embodiment, a body extension region of the second conductivity type is adjacent to the primary surface and spaced apart from the first trench. In another embodiment, a doped region of the first conductivity type is adjacent to the primary surface and abuts the first trench. In a further embodiment, the termination structure can include a second trench extending through a majority of the thickness of the semiconductor layer and a doped region is spaced apart from the first and second trenches.

Abstract: A circuit can include a pair of switching devices that are coupled to an intermediate switching node and another pair of switching devices that are coupled to an output node. The circuit can further include a magnetic element that can help to store energy when the circuit transitions from a low state to a high state and release the energy when the circuit transitions from a high state to a low state. The circuit can include a control device to allow synchronous operation between the different pairs of switching devices. The magnetic element can help to reduce voltage swings at the output switching node. Thus, switching devices within each of the pairs can be optimized to allow for better performance of the circuit.

Abstract: An electronic device can include a transistor having a drain region, a source region, a dielectric layer, and a gate electrode. The dielectric layer can have a first portion and a second portion, wherein the first portion is relatively thicker and closer to the drain region; the second portion is relatively thinner and closer to the source region. The gate electrode of the transistor can overlie the first and second portions of the dielectric layer. In another aspect, an electronic device can be formed using two different dielectric layers having different thicknesses. A gate electrode within the electronic device can be formed over portions of the two different dielectric layers. The process can eliminate masking and doping steps that may be otherwise used to keep the drain dopant concentration closer to the concentration as originally formed.

Abstract: A MOSFET having a stacked-gate super-junction design and novel termination structure. At least some illustrative embodiments of the device include a conductive (highly-doped with dopants of a first conductivity type) substrate with a lightly-doped epitaxial layer. The volume of the epitaxial layer is substantially filled with a charge compensation structure having vertical trenches forming intermediate mesas. The mesas are moderately doped via the trench sidewalls to have a second conductivity type, while the mesa tops are heavily-doped to have the first conductivity type. Sidewall layers are provided in the vertical trenches, the sidewall layers being a moderately-doped semiconductor of the first conductivity type. The shoulders of the sidewall layers are recessed below the mesa top to receive an overlying gate for controlling a channel between the mesa top and the sidewall layer. The mesa tops are coupled to a source electrode, while a drain electrode is provided on the back side of the substrate.

Abstract: A MOSFET having a stacked-gate super-junction design and novel termination structure. At least some illustrative embodiments of the device include a conductive (highly-doped with dopants of a first conductivity type) substrate with a lightly-doped epitaxial layer. The volume of the epitaxial layer is substantially filled with a charge compensation structure having vertical trenches forming intermediate mesas. The mesas are moderately doped via the trench sidewalls to have a second conductivity type, while the mesa tops are heavily-doped to have the first conductivity type. Sidewall layers are provided in the vertical trenches, the sidewall layers being a moderately-doped semiconductor of the first conductivity type. The shoulders of the sidewall layers are recessed below the mesa top to receive an overlying gate for controlling a channel between the mesa top and the sidewall layer. The mesa tops are coupled to a source electrode, while a drain electrode is provided on the back side of the substrate.

Abstract: An electronic device can include a semiconductor layer, an insulating layer overlying the semiconductor layer, and a conductive electrode. In an embodiment, a first conductive electrode member overlies the insulating layer, and a second conductive electrode member overlies and is spaced apart from the semiconductor layer. The second conductive electrode member has a first end and a second end opposite the first end, wherein each of the semiconductor layer and the first conductive electrode member are closer to the first end of the second conductive electrode member than to the second end of the second conductive electrode member. In another embodiment, the conductive electrode can be substantially L-shaped. In a further embodiment, a process can include forming the first and second conductive electrode members such that they abut each other. The second conductive electrode member can have the shape of a sidewall spacer.