Abstract: The present invention includes apparatus and methods to calibrate a phase detector and an analog-to-digital converter (ADC) offset and gain. In one such embodiment, an apparatus includes a phase detector to generate an error pulse and a reference pulse, a combiner to combine the pulses, and an ADC to receive the combined pulses, where the ADC has a full scale set by an average of the reference pulse. Still further, a calibration loop may be coupled between the output of the ADC and the phase detector to generate and provide a phase adjust signal to reduce or eliminate phase offsets. Other embodiments are described and claimed.

Abstract: The present invention includes apparatus and methods to calibrate a phase detector and an analog-to-digital converter (ADC) offset and gain. In one such embodiment, an apparatus includes a phase detector to generate an error pulse and a reference pulse, a combiner to combine the pulses, and an ADC to receive the combined pulses, where the ADC has a full scale set by an average of the reference pulse. Still further, a calibration loop may be coupled between the output of the ADC and the phase detector to generate and provide a phase adjust signal to reduce or eliminate phase offsets. Other embodiments are described and claimed.

Abstract: A method and system for representing stereoscopic motion imagery data having a right eye spatial data set and a left eye spatial data set. Each member of the left eye data set has a corresponding member in the right eye data set. The method determines correlated data and uncorrelated data between at least one left eye member and corresponding right eye member and compresses the correlated and the uncorrelated data. The method then forwards the compressed correlated and uncorrelated data at or below a predetermined channel capacity.

Abstract: A modular video processing system and methodology for processing a plurality of video assets having different asset properties in real-time to a common format compatible with a display device is described. The system includes a plurality of pipelined video processing modules wherein each operational pipelined video processing module performs a different configurable video processing function on one or more video asset frames. The system also includes a process control module for providing each operational pipelined video processing module with data for configuring the video processing module for a current frame and data for configuring the video processing module for a subsequent frame wherein each configuration is based on one or more asset properties for the video asset being processed. Each pipelined video processing module has a memory location for the configuration for the current frame and a memory location for the configuration for a subsequent frame.

Abstract: The present invention includes apparatus and methods to calibrate a phase detector and an analog-to-digital converter (ADC) offset and gain. In one such embodiment, an apparatus includes a phase detector to generate an error pulse and a reference pulse, a combiner to combine the pulses, and an ADC to receive the combined pulses, where the ADC has a full scale set by an average of the reference pulse. Still further, a calibration loop may be coupled between the output of the ADC and the phase detector to generate and provide a phase adjust signal to reduce or eliminate phase offsets. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for removing a DC offset from a loop having an amplifier coupled to receive an input signal, applying a selected slice level to the loop, and measuring an offset slice level at an output of the amplifier based on the applied selected slice level. The offset slice level may be stored and used to maintain the selected slice level of the amplifier.