Abstract: A processing system provides predicate data that indicates whether instructions processed by a processor pipeline should be executed by the pipeline. In architecture, the system of the present invention utilizes a register, a pipeline, and predicate circuitry. The pipeline includes a first stage and a second stage for processing instructions of a computer program. The predicate circuitry is configured to read a first predicate value from the register and to receive a second predicate value. The predicate circuitry may transmit the first predicate value read from the register to the first stage and then select between the first predicate value and the second predicate value. The predicate value selected by the predicate circuitry is transmitted to the second stage.

Abstract: A processing system provides predicate data that indicates whether instructions processed by a processor pipeline should be executed by the pipeline. In architecture, the system of the present invention utilizes a register, a pipeline, and predicate circuitry. The pipeline includes a first stage and a second stage for processing instructions of a computer program. The predicate circuitry is configured to read a first predicate value from the register and to receive a second predicate value. The predicate circuitry may transmit the first predicate value read from the register to the first stage and then select between the first predicate value and the second predicate value. The predicate value selected by the predicate circuitry is transmitted to the second stage.

Abstract: The present invention generally provides a system and method for writing data to a register file. In architecture, the system of the present invention utilizes a plurality of registers and a write port coupled to each of the registers. The write port receives a register identifier identifying one of the registers and receives a first signal, such as a bit of predicate data, a set signal, or a reset signal. The write port transmits the first signal and a decode signal to each of the registers. The write port is configured to assert the decode signal transmitted to the one register identified by the register identifier and to deassert the decode signal transmitted to the other registers. Each of the registers includes a set/reset latch and is configured to receive the first signal and the decode signal transmitted to it from the write port.

Abstract: An a new dynamic logic entry latch or new “ELAT” and a method to capture a static input and convert it to a single rail dynamic signal with improved functionality and reduced clock and input load. The new ELAT utilizes a pulsed evaluate concept to enable more complex pull-down stack configurations and other improvements. The pulsed evaluate concept uses a pulse generators driven by the static input and a clock waveform to evaluate the static input and appropriately drive field effect transmitters on the pull-down stack. Utilizing multiple-input pulse generators or multiple pulse generators, the new ELAT can allow a wider variety of input functions and their inverses to be constructed without over-loading the pull-down stack.