Abstract: A timing control arrangement that dynamically controls the distribution of iming information in a distributed digital communication system. A reference timing signal is distributed from a reference master node to all other nodes in the system. The distribution is accomplished on a dynamic basis without the use of a central control. Each node is connected by links to at least one other node and each node receives timing signals from all of the links to which it is connected. Each node selects one of these signals as its timing reference by scanning the various signals it receives to identify the one signal that is applied via a link path that is the "closest" to the master reference node as indicated by information specifying the number of intermediate nodes through which the timing signal has traveled from the reference node to reach the receiving node.

Abstract: Apparatus for and a method of inserting circuit switch information and packetized data into different time slots of a time division multiplexed bus. A memory having a location individual to each time slot is written with information specifying whether the time slot individual to each location is to serve circuit switch information or packet data. The readout of each memory location during the occurrence of it's associated time slot controllably effects the application of either the circuit switch information or the packet data to the bus. Packet data can be inserted into each time slot not currently being used by the circuit switch. A special information bit is inserted into each time slot to specify whether the remainder of the bits of the time slot represents circuit switch or packet information. The information bit is used by receiving apparatus to steer the bits of each time slot to either a receiving circuit switch or a receiving packet switch.

Abstract: Apparatus for and a method of inserting circuit switch information and packetized data into different time slots of a time division multiplexed bus. A memory having a location individual to each time slot is written with information specifying whether the time slot individual to each location is to serve the circuit switch information or the packet data. The readout of each memory location during the occurrence of it's associated time slot controllably effects the application of either the circuit switch information or the packet data to the bus.

Abstract: There is disclosed a clock circuit for a PBX system that uses phase locked loop technology to perform synchronization between two input signals. The system can switch between different reference sources without introducing error and without requiring the entire circuit to become realigned with the phase of the newly selected reference signal. This is accomplished with a phase build-out circuit that uses a phase locked loop divider to change the phase of the internal control signal to match the phase of the newly selected reference thereby eliminating timing changes on the system clock bus. The system can also be used to change between redundant clock circuits.

Abstract: Presently available printed wiring board backplanes used in switching systems and the like are wired at the time of manufacture to enable only a fixed number of groups of circuit boards to communicate with each other. This limitation prevents a backplane from having the capability of serving a varying number of groups of boards. The present invention enables a backplane to have the capability of serving a variable number of groups of boards. The number of groups that can be served by a given backplane need not be fixed when the backplane is designed and manufactured. Each backplane of the present invention comprises backplane bus conductors and board conductors. The boards are effectively a part of the bus. The use of a first type of board in a backplane connector continues the bus to the adjacent connector. The use of a second type of board terminates the bus and does not extend it beyond the connector into which the second type of board is inserted.

Abstract: Synchronization facilities are disclosed for maintaining error free timing of a digital system when control of the system timing is switched between a plurality of clock sources. The signal of each source is applied to an associated counter divider whose output is applied to switch facilities which extend the output of only one divider at a time as a reference clock source to the digital system. The dividers for the other sources are forcibly reset each time the divider of the reference source advances from its all 1s to its reset (all 0s) position. This maintains the output signals of all dividers in phase with each other to prevent disturbances to the digital system when its timing is switched between clock sources.

Abstract: The subject invention is a precision controlled frequency synthesizer which is capable of precisely adjusting the frequency of an output signal to maintain a desired frequency difference between an input and output signal regardless of the stability of the frequency of an input signal. The synthesizer comprises the basic elements of a phase locked loop (PLL) type circuit. The PLL circuit portion detects the actual frequency difference, a value A, between the input and output signals. A reference source provides a desired frequency difference, a value D, which represents the frequency difference between a stable input frequency and a desired output frequency. The difference between the frequency difference values A and D serves as the amount of adjustment to the frequency of the output signal. This adjustment represents the amount of compensation necessary to maintain a specified frequency relationship between the input and output signals.

Abstract: A frequency and phase comparator circuit for determining the frequency difference between a reference signal of a known frequency and a variable signal of unknown frequency. The subject circuit monitors the two signals and detects the occurrence of phase shifts between the two signals. In particular, this circuit detects phase shifts of 180 degrees and 360 degrees and records a full slip indication with each occurrence of a 360 degree phase shift. These phase shifts indicate that at some point in time during transmission, the two signals were out of phase and not of exact frequency. In addition, the subject circuit provides a direction of drift indication with each 180 degree shift. These direction indications are output following a 360 degree phase shift or full slip and are determinative of the relative frequencies of the two signals by designating whether the frequency of the variable signal is higher or lower than that of the reference signal over the duration of the full slip.

Abstract: Circuitry allocates requests for demand-shared bus access among a plurality of service requesting ports. During bus contention time, each requesting port synchronously and sequentially applies the digits of its assigned unique priority code to the bus beginning with the most significant digit. After the application of all digits, only the requesting port having the highest code remains in contention and it seizes the bus. Increased flexibility in port preference is provided by the use of a plurality of status flip-flops in each port for generating dynamic port parameter bits. The generated parameter bits are normally applied to the bus as the most significant bits of a dynamic port priority code during contention time. However, the selective application of a mask signal to a mask conductor during contention time causes each requesting port to prevent any parameter bits from being applied to the bus as long as the mask signal remains.

Abstract: Circuitry is disclosed for allocating requests for demand-shared bus access among a plurality of service requesting ports. During bus contention time, each requesting port synchronously and sequentially applies the digits of its assigned unique priority code to the bus beginning with the most significant digit. After the application of all digits, only the requesting port having the highest code remains in contention and it seizes the bus. A plurality of status flip-flops is provided in each port for generating port parameter bits. The generated parameter bits are applied to the bus as the most significant bits of a dynamic port priority code during contention time. However, the selective application of a mask signal to a mask conductor during contention time causes each requesting port to ignore any parameter bits on the bus as long as the mask signal remains. This returns control of the port preference to any unmasked parameter bits and to the assigned port priority codes.

Abstract: Circuitry is disclosed for allocating requests for demand-sharing bus access among a plurality of service requesting ports. During bus contention time, each requesting port synchronously and sequentially applies the digits of its assigned unique priority code to the bus beginning with the most significant digit. After the application of all digits, only the requesting port having the highest code remains in contention and it seizes the bus. The present invention provides flexibility in port preference by the use of a plurality of status flip-flops in each port for generating dynamic port parameter bits. The generated parameter bits are normally applied to the bus as the most significant bits of a dynamic port priority code during contention time. The state of the status flip-flops is controlled by circuitry which counts the number of packets of a specified size currently stored in the buffer memory of each port.

Abstract: A man-machine interface is disclosed for translating discrete hand positions into electrical signals representing alpha-numeric characters. The interface comprises a glove having sensors positioned with respect to the hand for detecting the flex of finger joints and sensors for detecting the contact between various portions of the hand. Additional sensors detect the movement of the hand with respect to a gravitational vector and a horizontal plane of reference. Further additional sensors detect the twisting and flexing of the wrist. The additional sensors are associated with prescribed mode signals which determine whether subsequently formed or priorly formed character specifying hand positions are to be entered for transmission. The alpha-numeric characters associated with the formed character specifying hand positions are transmitted only when the appropriate mode signal results.