Abstract: A digital computer architecture specifically tailored for implementing a neural network. Several simultaneously operable processors (10) each have their own local memory (17) for storing weight and connectivity information corresponding to nodes of the neural network whose output values will be calculated by said processor (10). A global memory (55,56) is coupled to each of the processors (10) via a common data bus (30). Output values corresponding to a first layer of the neural network are broadcast from the global memory (55,56) into each of the processors (10). The processors (10) calculate output values for a set of nodes of the next higher-ordered layer of the neural network. Said newly-calculated output values are broadcast from each processor (10) to the global memory (55,56) and to all the other processors (10), which use the output values as a head start in calculating a new set of output values corresponding to the next layer of the neural network.

Abstract: A telemetry data processor for processing extremely high bandwidth data such as that associated with telemetry from spacecraft. A demultiplexer (1) distributes the data onto several channels (CHl through CHn), each comprising a (preferably split-cycle synchronous) processing bus (BUSl through BUSn). Processing can occur on each of the n buses simultaneously. Several processor modules (P boards) are directly coupled to each processing bus, with each P board directly coupled to two buses. Several memory modules (M boards) are directly coupled to each processing bus, with each M board directly coupled to two buses. The functions and architectures of the P boards and M boards are described, along with those of D boards (disk controller modules) and I boards (modules for interfacing the telemetry data processor with its outside environment, which may comprise local area networks, peripherals, gateways, etc.).