Abstract: Disclosed is a system and method for using a programmable sequencer to produce a required command for a particular standard, or format, being used by the PCIe disk drive. A PCIe disk drive may support a different standard, or format. A mix of any number of different standards, or formats, is permitted in the system and method. For each message, a different set of instructions can be selected for the conversion process.

Abstract: Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature checked.

Abstract: Disclosed is a system and method for using a programmable sequencer to produce a required command for a particular standard, or format, being used by the PCIe disk drive. A PCIe disk drive may support a different standard, or format. A mix of any number of different standards, or formats, is permitted in the system and method. For each message, a different set of instructions can be selected for the conversion process.

Abstract: Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature checked.

Abstract: Disclosed is a storage device interface. The storage device interface includes a plurality of PCIe device request engines. These PCIe device request engines receive I/O commands formatted for a respective one of a plurality of PCIe storage device communication standards. The storage device interface also includes a plurality of PCIe device completion engines. These PCIe device completion engines receive notifications of command completions from a plurality of PCIe storage devices that communicate using the aforementioned plurality of PCIe storage device communication standards. These notifications are validated. If an error is detected, processing of notifications of command completions associated with that device are blocked until the error is resolved. The plurality of PCIe device request engines and the PCIe device completion engines operate concurrently to process received I/O commands and received command completions.

Abstract: Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. If an error is detected, a data integrity signature may be corrupted. A completion signature may be written. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature and completion signature checked.

Abstract: Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature checked.

Abstract: Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature checked.

Abstract: Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature checked.

Abstract: Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature checked.

Abstract: Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. If an error is detected, a data integrity signature may be corrupted. A completion signature may be written. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature and completion signature checked.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. To optimize memory bandwidth and reduce memory latency, various techniques are implemented in the present RAID system. Present techniques include providing dual memory arbiters, sorting read cycles by chip select or bank address, providing programmable upper and lower boundary registers to facilitate programmable memory mapping, and striping and interleaving memory data to provide a burst length of one.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.

Abstract: The control logic for a hot-pluggable memory cartridge for use in a redundant memory system. To implement a hot-pluggable memory cartridge in a redundant memory system, control logic to control the sequence of events for powering-up and powering-down a memory cartridge is provided.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. To optimize memory bandwidth and reduce memory latency, various techniques are implemented in the present RAID system. Present techniques include providing dual memory arbiters, sorting read cycles by chip select or bank address, providing programmable upper and lower boundary registers to facilitate programmable memory mapping, and striping and interleaving memory data to provide a burst length of one.

Abstract: A technique for resynchronizing a memory system. More specifically, a technique for resynchronizing a plurality of memory segments in a redundant memory system after a hot-plug event. After a memory cartridge is hot-plugged into a system, the memory cartridge is synchronized with the operational memory cartridges such that the memory system can operate in lock step. A refresh counter in each memory cartridge is disabled to, generate a first refresh request to the corresponding memory segments in the memory cartridge. After waiting a period of time to insure that regardless of what state each memory cartridge is in when the first refresh request is initiated all cycles have been completely executed, each refresh counter is re-enabled, thereby generating a second refresh request. The generation of the second refresh request to each of the memory segments provides synchronous operation of each of the memory cartridges.

Abstract: A method of adding memory capacity to a computer system. The computer system comprises a redundant memory system including a plurality of memory cartridges. By powering-down a memory cartridge, adding an additional memory module to the memory cartridge, and powering-up the memory cartridge for each memory cartridge in the system, the system can transition from a redundant mode of operation to a non-redundant mode of operation for each power-down, thus allowing the computer system to remain functional during the addition of the memory module. Alternatively, memory cartridges with higher memory capacity than those currently present in the computer system can be used to replace existing memory cartridges in the computer system, using the same techniques.

Abstract: A system and technique for correcting data errors in a memory device. More specifically, data errors in a memory device are corrected by scrubbing the corrupted memory device. Generally, a host controller delivers a READ command to a memory controller. The memory controller receives the request and retrieves the data from a memory sub-system. The data is delivered to the host controller. If an error is detected, a scrub command is induced through the memory controller to rewrite the corrected data through the memory sub-system. Once a scrub command is induced, an arbiter schedules the scrub in the queue. Because a significant amount of time can occur before initial read in the scrub write back to the memory, an additional controller may be used to compare all subsequent READ and WRITE commands to those scrubs scheduled in the queue.