Abstract: A graphics processing device generates control lists for controlling processing of 3D graphics. Control lists comprise primitive data for the 3D graphics, pointers to primitive data and control data. Tags that correspond to records within the control lists may be utilized for the control of processing. The graphics processing device may comprise a 3D pipeline comprising parallel processors. Processing is performed on a tile by tile basis and comprises a tile binning phase and/or a tile rendering phase. The two phases of processing may be performed in parallel on different sets of data. Control lists comprise a main list and/or sub-lists, for example, tile lists. Control lists may comprise links to other lists. Processing control may advance through the control lists without interaction from a driver and/or from a processor that is external to the graphics processing device.

Abstract: Image data may be processed via one or more stages by a hardware image sensor pipeline (ISP) wherein one or more software processing steps may be inserted at any point within the hardware ISP. Output from any stage of the hardware ISP may be stored in memory. Stored hardware ISP output may be retrieved from memory and processed via one or more software processes. Results from the one or more software processes may be stored in memory and communicated to any stage of the hardware ISP for additional processing. In this regard, the hardware ISP and one or more processors may simultaneously process portions of image data. In addition, the hardware ISP and the one or more processors may be integrated within a chip.

Abstract: In a graphics processing device, a plurality of processors write fragment shading results for order-dependent data to a buffer, according to the order in which the data is received. Fragment shading results for order-neutral data is written to the buffer one batch at a time. The order-dependent data comprises spatially overlapping data. Order-neutral data may not overlap. A scheduler controls the order of reception of one batch of data at a time by the processors. The order for receiving the order-dependent data may be determined. The plurality of processors may process the data in parallel. A writing order for writing results to a buffer from the processing in parallel, may be enforced. A portion of the processors may be instructed to wait before writing results to the buffer in a specified order. Processors signal when writing results to the buffer is complete.

Abstract: A complex curved primitive is decomposed into curvy RHTs comprising a curved portion and horizontal and vertical lines. Pixel rows covered by curvy RHTs are determined. RHT pixels covered by the curved primitive are determined with counters. Tile based color rendering is performed for covered pixels. The primitive path is decomposed into Bezier curves. Curvy RHTs may overlap and may cover pixels that are not covered by the curved primitive. Pixel rows are located by traversing an RHT path and the direction of traversing may determine pixel counts. Pixel coverage and tile coverage information is stored in memory. Pixels may be rendered in parallel. The curved primitive is rendered in a tile binning phase and a tile rendering phase. Tile rendering comprises a pixel coverage first pass which determines pixels covered by said curved primitive and a color rendering second pass.

Abstract: A method and system are provided in which one or more processors and/or circuits are operable to generate position information for a plurality of primitives utilizing a coordinate shader, one or more lists based on the generated position information, and rendering information for the plurality of primitives utilizing a vertex shader and the generated one or more lists. The generated one or more lists may comprise indices associated with one or more primitives from the plurality of primitives and with one or more tiles from a plurality of tiles in a screen plane. The position information and the one or more lists may be generated during a first rendering phase, and the rendering information may be generated during a second rendering phase different from the first rendering phase. The coordinate shader may perform a subset of the operations supported by the vertex shader.

Abstract: A graphics processing device may generate coordinates for vertices of graphics primitives in a view-space. Tiles are defined within the view-space and are associated with tile lists. Primitives and/or vertices which overlap a tile are determined. Tile lists comprise differentially encoded indices and/or spatial coordinates for overlapping primitives. The differential encoding may or may not be byte aligned. During tile mode graphics rendering, tile lists are utilized to reference vertex attributes and/or primitives. Graphics rendering comprises a tile binning phase and a tile rendering phase. The primitives may comprise a triangle and/or joined triangles that share one or more vertices. For multiple joined primitives, information about shared vertices may be encoded without repetition for each primitive. Coordinates and/or corresponding weights for new vertices are encoded in a tile list and utilized for interpolating properties of the new vertices based on attributes of the original vertices.

Abstract: A complex curved primitive is decomposed into curvy RHTs comprising a curved portion and horizontal and vertical lines. Pixel rows covered by curvy RHTs are determined. RHT pixels covered by the curved primitive are determined with counters. Tile based color rendering is performed for covered pixels. The primitive path is decomposed into Bezier curves. Curvy RHTs may overlap and may cover pixels that are not covered by the curved primitive. Pixel rows are located by traversing an RHT path and the direction of traversing may determine pixel counts. Pixel coverage and tile coverage information is stored in memory. Pixels may be rendered in parallel. The curved primitive is rendered in a tile binning phase and a tile rendering phase. Tile rendering comprises a pixel coverage first pass which determines pixels covered by said curved primitive and a color rendering second pass.

Abstract: In a graphics processing device, a plurality of processors write fragment shading results for order-dependent data to a buffer, according to the order in which the data is received. Fragment shading results for order-neutral data is written to the buffer one batch at a time. The order-dependent data comprises spatially overlapping data. Order-neutral data may not overlap. A scheduler controls the order of reception of one batch of data at a time by the processors. The order for receiving the order-dependent data may be determined. The plurality of processors may process the data in parallel. A writing order for writing results to a buffer from the processing in parallel, may be enforced. A portion of the processors may be instructed to wait before writing results to the buffer in a specified order. Processors signal when writing results to the buffer is complete.

Abstract: A method and system are provided in which a first instruction associated with a graphics rendering operation may be executed in a shader processor, the shader processor may receive result information associated with an intermediate portion of the graphics rendering operation performed by a peripheral device operably coupled to a register file bus in the shader processor, and the shader processor may execute a second instruction associated with the graphics rendering operation based on the received result information. The register file bus may be utilized for handling execution of intermediate instructions associated with the intermediate portion of the graphics rendering operation. The peripheral device may be accessed via one or more register file addresses associated with the peripheral device. The peripheral device may be operably coupled to the shader processor via a FIFO.

Abstract: A graphics processing device generates control lists for controlling processing of 3D graphics. Control lists comprise primitive data for the 3D graphics, pointers to primitive data and control data. Tags that correspond to records within the control lists may be utilized for the control of processing. The graphics processing device may comprise a 3D pipeline comprising parallel processors. Processing is performed on a tile by tile basis and comprises a tile binning phase and/or a tile rendering phase. The two phases of processing may be performed in parallel on different sets of data. Control lists comprise a main list and/or sub-lists, for example, tile lists. Control lists may comprise links to other lists. Processing control may advance through the control lists without interaction from a driver and/or from a processor that is external to the graphics processing device.

Abstract: A graphics processing device may generate coordinates for vertices of graphics primitives in a view-space. Tiles are defined within the view-space and are associated with tile lists. Primitives and/or vertices which overlap a tile are determined. Tile lists comprise differentially encoded indices and/or spatial coordinates for overlapping primitives. The differential encoding may or may not be byte aligned. During tile mode graphics rendering, tile lists are utilized to reference vertex attributes and/or primitives. Graphics rendering comprises a tile binning phase and a tile rendering phase. The primitives may comprise a triangle and/or joined triangles that share one or more vertices. For multiple joined primitives, information about shared vertices may be encoded without repetition for each primitive. Coordinates and/or corresponding weights for new vertices are encoded in a tile list and utilized for interpolating properties of the new vertices based on attributes of the original vertices.

Abstract: A method and system are provided in which one or more processors and/or circuits are operable to generate position information for a plurality of primitives utilizing a coordinate shader, one or more lists based on the generated position information, and rendering information for the plurality of primitives utilizing a vertex shader and the generated one or more lists. The generated one or more lists may comprise indices associated with one or more primitives from the plurality of primitives and with one or more tiles from a plurality of tiles in a screen plane. The position information and the one or more lists may be generated during a first rendering phase, and the rendering information may be generated during a second rendering phase different from the first rendering phase. The coordinate shader may perform a subset of the operations supported by the vertex shader.

Abstract: Image data may be processed via one or more stages by a hardware image sensor pipeline (ISP) wherein one or more software processing steps may be inserted at any point within the hardware ISP. Output from any stage of the hardware ISP may be stored in memory. Stored hardware ISP output may be retrieved from memory and processed via one or more software processes. Results from the one or more software processes may be stored in memory and communicated to any stage of the hardware ISP for additional processing. In this regard, the hardware ISP and one or more processors may simultaneously process portions of image data. In addition, the hardware ISP and the one or more processors may be integrated within a chip.

Abstract: Image data may be processed via one or more stages by a hardware image sensor pipeline (ISP) wherein one or more software processing steps may be inserted at any point within the hardware ISP. Output from any stage of the hardware ISP may be stored in memory. Stored hardware ISP output may be retrieved from memory and processed via one or more software processes. Results from the one or more software processes may be stored in memory and communicated to any stage of the hardware ISP for additional processing. In this regard, the hardware ISP and one or more processors may simultaneously process portions of image data. In addition, the hardware ISP and the one or more processors may be integrated within a chip.

Abstract: Methods and systems for processing images using variable size tiles are disclosed and may include receiving raw image data for processing and dividing the received raw image data into a plurality of variable size tiles for processing. The variable size tiles may be sequentially processed. Each of the variable size tiles may comprise a plurality of lines. A size of the variable size tiles may be adjusted based on a distortion in a corresponding region of the raw image data. The variable size tiles may be processed in an image sensor pipeline. A current variable size tile may overlap at least one neighboring variable size tile. At least one neighboring variable size tile may include one or more of: above the current variable size tile, below the current variable size tile, left of the current variable size tile, and right of the current variable size tile.

Abstract: In an embodiment of the invention, images are processed within a mobile device. Image data may be divided into variable size tiles and processed in steps or stages on a per tile basis within a hardware image sensor pipeline. The processing steps or stages may comprise one or more distortion correction steps. A portion of the variable size tiles may be processed via software within a processor. In this regard, output from any portion of the ISP may be stored in RAM and subsequently retrieved for software processing. The results from software processing may be stored in RAM and communicated back to any point within the hardware ISP for additional processing. The hardware ISP and the processor via software may simultaneously process different portions of the variable size tiles.

Abstract: Methods and systems for coupling a 3D pipeline to a generic video processing unit (VPU) are disclosed. Aspects of one method may include concurrently accessing different portion of stored graphics data by the generic VPU and the 3D pipeline within a chip. The graphics data may be processed by the VPU and the 3D pipeline. The VPU may be able to perform, for example, vector processing and scalar processing. The vector processing may be performed on the graphics data by a plurality of pixel processors. The graphics data may be stored and/or accessed in a vector register file (VRF), which may comprise a plurality of banks. Graphics data may be stored as a plurality of vectors in each of the banks in the VRF. The graphics data may be stored and/or read a vector at a time by the VPU and the 3D pipeline. Each vector may comprise, for example, 512 bits.

Abstract: Methods and systems for processing video data are disclosed herein and may include determining a first video format associated with video data to be displayed on a first video display communicatively coupled to a single mobile multiple media processor that supports a plurality of display formats. The single mobile multiple media processor may be integrated within a mobile device. An amount of the video data that is transferred from memory to the first video display, by a DMA controller, may be restricted based on the determined first video format associated with the video data to be displayed on a first video display. Only the restricted amount of the video data that is to be displayed by the first video display may be transferred from the memory to the first video display by the DMA controller.