Abstract: Improved shallow trench isolation (STI) techniques are provided for semiconductor devices. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a substrate, a first trench in the substrate, and a second trench in the substrate. A first transistor region in the substrate is adjacent to and between the first and second trenches. A silicon dioxide liner substantially lines the first and second trenches. A silicon nitride liner is on the silicon dioxide liner in the first trench but not on the silicon dioxide liner in the second trench. A dielectric material fills the first and second trenches.