Patents by Inventor Gary L. Beene

Gary L. Beene has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6320255
    Abstract: The invention relates to a flexible and cost-effective method for fabricating customized rerouting metallization of the circuit contact pads. Localized depositions of insulating as well as conducting paths are provided with the capability for manufacturing multi-layered networks of interconnection. In a gas-filled chamber, either a focused laser, or an unfocussed lased impinging through a mask, is used to locally heat selected areas of the chip surface. The gas decomposes on the heated areas, depositing insulating or conducting material precisely on the heated surface areas, respectively. With this additional flexibility for product design and assembly, a number of interesting new products can now be fabricated which are in demand in both commercial and military markets.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: November 20, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Earl Terrill, John David Drummond, Gary L. Beene
  • Patent number: 5673478
    Abstract: A method and an apparatus for I/O reroute include the use of reroute traces (16) and overhangs (20). The reroute traces (16) and overhangs (20) are formed using thick film deposition on dies that have been cut from a wafer.
    Type: Grant
    Filed: November 16, 1995
    Date of Patent: October 7, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Gary L. Beene, Robert E. Terrill
  • Patent number: 4943844
    Abstract: A chip carrier with improved packing density, wherein at least one layer of chips is bonded not directly to the substrate, but rather to a heat plate which attaches over the chip cavity and inside the hermetic sealing lid. The heat plate has openings in it to permit attachment of the leads from the chips in the upper layer to bond pads on a bonding ledge inside the cavity of the chip carrier, after the heat plate is emplaced. Each bonding ledge is preferably made somwhat wider than it would otherwise be, and the leads from multiple layers of chips are preferably bonded onto the same bonding ledge.
    Type: Grant
    Filed: November 22, 1985
    Date of Patent: July 24, 1990
    Assignee: Texas Instruments Incorporated
    Inventors: Alex A. Oscilowski, Charles E. Williams, Gary L. Beene, Peter Zogas
  • Patent number: 4903120
    Abstract: A chip carrier with multiple through hole vias in its hermetic sealing lid. One or more chips is mounted on the inner surface of that lid. The lid contains multiple through vias, and the semiconductor chip on the inner surface of the lid is bonded to the vias in the lid by TAB strips or (optionally) by wire bonds. The vias in the lid connect these leads through to contacts on the outer surface of the package. These contacts can than be connected to (using interconnect structures such as TAB strips, or printed wiring boards, or discretionary wiring), to provide circuit interconnection. Preferably low-power-dissipation chips are mounted on the inner surface of the lid in this fashion, with higher-power-dissipation chips mounted on the bottom surface of the chip cavity.
    Type: Grant
    Filed: November 22, 1985
    Date of Patent: February 20, 1990
    Assignee: Texas Instruments Incorporated
    Inventors: Gary L. Beene, Thomas D. Petrovich, Charles E. Williams