Abstract: A counter includes an array of memory cells arranged in groups of memory cells, each group designating a counting decade, wherein each group of memory cells includes first and second word strings, each capable of storing a data word, and a fault flag, capable of indicating which word string contains the data word; sensing means coupled to the memory array for checking the status of the memory cells and for generating fault signals upon detection of a fault in a memory cell; logic means coupled to the memory cells and to the sensing means for selecting the first or second word string in response to a fault signal; wherein upon detection of a fault in a first word string, the data word is written into the second word string; and a central shifting unit coupled to the memory array for reading a data word stored in a word string into the shifting unit, incrementing the data word, and writing the incremented data word into its respective word string.

Abstract: A memory cell comprising a bistable latch having first and second nodes, at least two non-volatile transistors (NV1, NV2) each having a source, a drain and a control gate, the control gates being connected to the first node (NODE 1) and one of the source and drain of each transistor being connected to the second node (NODE 2), each non-volatile transistor (NV1, NV2) further having a substrate and a floating gate between the control and the substrate, and switching means (N1, N2, TG1) for enabling the transistors to be checked in circuit.