Abstract: A gray code is produced from a minimum of gate logic by making available and monitoring master outputs of master-slave latch pairs, where the latch pairs are arranged to form a cascading chain of toggle flip-flop stages. The least significant bit through one less than the most significant bit in the gray code is supplied by the master latch outputs and the most significant gray code bit is supplied by the slave latch output of the last toggle stage in the chain.

Abstract: The invention comprises a gallium arsenide driver with float capability for logic high and logic low signals including logic means for receiving an input signal and providing logic high and low signals therefrom. Level shift means responsive to the high and low signals downshift the voltage levels thereof. Common gate means responsive to the downshifted signal voltage levels amplify these signals, and output source-follower means responsive to the amplified signals provide output signals to a pad.

Abstract: The present invention provides a unique circuit and layout methods for improving upon series redundant circuits. A substitution device, comprising a pair of series connected N or P FETs for respective single FETs, can be further hardened or enhanced against cosmic rays, particles, etc. by spacing the P FETs a predetermined distance apart so that an ion or other particle cannot strike or affect both channels simultaneously, thus avoiding upset. When these devices are placed in cells (i.e., ASIC) in logic or the like circuits, the predetermined spacing is related to cell height. Also, alignment of the gates of the substitution device on a common axis minimizes the window of a satellite through which a particle could effectively strike the common gate axis possibly to upset both gates.

Abstract: The invention provides small size, high speed data latches comprising memory cells that are fabricated according to a Gallium Arsenide (GaAs) process. The memory cells are implemented by a relatively few number of depletion metal semiconductor field effect transistors (MESFETs), saturated resistors and diodes. A common gate MESFET is utilized in each memory cell configuration as part oif a non-inverting positive feedback path to provide the gain necessary for bistable operation.

Abstract: A gallium arsenide input receiver and method modify a conventional voltage level shifter circuit at its input to adapt it to operate on the lower gallium arsenide input voltages. A gallium arsenide depletion common gate amplifier FET receives the lower range of input voltages and turns off when the input signal equals or overcomes its V.sub.p voltage. This causes a pull-up device to apply the full voltage supply to the input of the voltage level shifter circuit, thereby enhancing the input signal voltage level to that originally used for the level shifter circuit. In a second embodiment of voltage compensation circuit is added to compensate for process variations in the V.sub.p voltage for the common gate amplifier FET. Reference voltage is developed by a circuit including a compensating depletion FET having a V.sub.p similar to that of the common gate FET which compensates for changes in the common gate V.sub.

Abstract: A tristate driver circuit is provided having a logic input signal, to produce a logic 1 output level or a logic 0 output level, and a float input signal, to produce float state operation. The circuit comprises a first logic gate powered by a first buffer switch, a second logic gate powered by a second buffer switch, an output driver having a first driver input from the output of the first gate and a second signal driver input from the output of the second gate; the first and second buffer switches dissipating the greatest circuit power during the circuit float state operation, and means, coupled to the first and second buffer switches and to the source of float signal input signal, for interrupting power to the first and second buffer switches responsive to onset of the float state operation.

Abstract: An improved layout for controlling the channel length of silicon gate, enhancement and depletion pull-up field effect transistor devices. The improved layout enables a transistor device to be fabricated with minimal size and at minimum channel length tolerance.

Abstract: An "on chip" substrate bias generator circuit to automatically compensate for threshold variations of devices that form a MOS circuit. The substrate bias generator includes a voltage doubler (or trippler) to develop a wide range of negative bias voltage to be fed back via the substrate to the MOS circuit to provide uniform bias control of the circuit devices.

Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of only desired portions of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliabilty. The process allows the simultaneous doping of two or more regions resulting in uniformity of device characteristics.

Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and self-aligned contacts for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different oxidation and etch characteristics permits selective oxidation of only desired portions of the structure without need for masking, and removal of selected material from desired locations by batch removal processes again without use of masking. The process and resulting structure affords inherently self-aligned gates and contacts for FET devices and conducting lines.

Abstract: An improved, compact, power saving data latch having utilization as a synchronizer circuit or as a circuit to sample and store input data for subsequent signal processing. The presently improved data latch is fabricated by means including a static flip-flop cell. A transmission gate is connected between an input terminal of the flip-flop cell and a source of input data. A source of clock signals is connected to another input terminal of the flip-flop cell and to a control electrode of the transmission gate to control the conductivity of the transmission gate and the sampling of input data by the flip-flop cell.

Abstract: An electronically programmable frequency correction arrangement. The frequency of a source input signal is compared to a desired frequency. Pulse stuffing techniques are utilized by which a number of pulses comprising a frequency correction signal are selectively added to the input signal so as to accurately adjust the source frequency to the desired frequency.

Abstract: An integrated circuit is disclosed providing the logic to generate a unique binary coded numerical counting sequence and a corresponding decoded segment select sequence to subsequently activate particular segments comprising a display pattern at predetermined times. A minimum number of logic input terms and respective logic gates are required to implement the instant sequence to thereby reduce the space consumed by the circuit and the cost thereof.