Patents by Inventor Gary L. Howe

Gary L. Howe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12277963
    Abstract: Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.
    Type: Grant
    Filed: January 3, 2024
    Date of Patent: April 15, 2025
    Inventors: Gary L. Howe, Miles S. Wiscombe, James S. Rehmeyer, Eric J. Stave
  • Patent number: 12197264
    Abstract: Methods, systems, and devices for power management for a memory device are described. For example, a memory device may include one or more memory dies and may be configured to operate using a first supply voltage and a second supply voltage. The first supply voltage may be associated with a first defined voltage range, and the second supply voltage may be associated with a second defined voltage range. The memory device may include a power management integrated circuit (PMIC) that is coupled with the one or more memory dies and provides the supply voltages to the one or more memory dies. The PMIC may be configured to provide, to the one or more memory dies, a first voltage that is within the first defined voltage range as the first supply voltage and a second voltage that is outside the second defined voltage range as the second supply voltage.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: January 14, 2025
    Assignee: Micron Technology, Inc.
    Inventors: James S. Rehmeyer, Gary L. Howe, Miles S. Wiscombe, Eric J. Stave
  • Publication number: 20240420746
    Abstract: A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.
    Type: Application
    Filed: August 26, 2024
    Publication date: December 19, 2024
    Inventors: Brian W. Huber, Scott E. Smith, Gary L. Howe
  • Patent number: 12087394
    Abstract: A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: September 10, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Brian W. Huber, Scott E. Smith, Gary L. Howe
  • Publication number: 20240281387
    Abstract: Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.
    Type: Application
    Filed: March 11, 2024
    Publication date: August 22, 2024
    Inventors: Debra M. Bell, Vaughn N. Johnson, Kyle Alexander, Gary L. Howe, Brian T. Pecha, Miles S. Wiscombe
  • Publication number: 20240221813
    Abstract: Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.
    Type: Application
    Filed: January 3, 2024
    Publication date: July 4, 2024
    Inventors: Gary L. Howe, Miles S. Wiscombe, James S. Rehmeyer, Eric J. Stave
  • Publication number: 20240176487
    Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.
    Type: Application
    Filed: September 8, 2023
    Publication date: May 30, 2024
    Inventors: Thanh K. Mai, Gary L. Howe, Daniel B. Penney
  • Publication number: 20240168656
    Abstract: Apparatuses and methods for memory array accessibility can include an apparatus with an array of memory cells. The array can include a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus. The array can include a second portion accessible to the devices external to the apparatus. The array can include a number of registers that store row address that indicate which portion of the array is the first portion. The apparatus can include the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.
    Type: Application
    Filed: January 29, 2024
    Publication date: May 23, 2024
    Inventors: Daniel B. Penney, Gary L. Howe
  • Publication number: 20240161809
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to provide row clear features. In some embodiments, the memory device may receive a command from a host device directed to a row of a memory array included in the memory device. The memory device may determine that the command is directed to two or more columns associated with the row, where each column is coupled with a group of memory cells. The memory device may activate the row to write the two or more columns using a set of predetermined data stored in a register of the memory device. Subsequently, the memory device may deactivate the word line based on writing the set of predetermined data to the two or more columns.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 16, 2024
    Inventors: Miles S. Wiscombe, Scott E. Smith, Gary L. Howe, Brian W. Huber, Tony M. Brewer
  • Patent number: 11934326
    Abstract: Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.
    Type: Grant
    Filed: August 6, 2022
    Date of Patent: March 19, 2024
    Inventors: Debra M. Bell, Vaughn N. Johnson, Kyle Alexander, Gary L. Howe, Brian T. Pecha, Miles S. Wiscombe
  • Publication number: 20240087621
    Abstract: A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 14, 2024
    Inventors: Brian W. Huber, Scott E. Smith, Gary L. Howe
  • Patent number: 11908509
    Abstract: Methods, apparatuses, and systems related to operations for managing the quality of an input signal received by a device and for providing feedback in real-time. A controller can provide a reference signal to the device for the input quality check. The memory can implement the input quality check by counting the number of transitions of the reference signal for a set time period and store the resulting count value(s). The memory can use the count value(s) to determine a condition or a quality for the reference signal.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: John E. Riley, Scott E. Smith, Jennifer E. Taylor, Gary L. Howe
  • Patent number: 11881245
    Abstract: Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: January 23, 2024
    Inventors: Gary L. Howe, Miles S. Wiscombe, James S. Rehmeyer, Eric J. Stave
  • Patent number: 11881251
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to provide row clear features. In some embodiments, the memory device may receive a command from a host device directed to a row of a memory array included in the memory device. The memory device may determine that the command is directed to two or more columns associated with the row, where each column is coupled with a group of memory cells. The memory device may activate the row to write the two or more columns using a set of predetermined data stored in a register of the memory device. Subsequently, the memory device may deactivate the word line based on writing the set of predetermined data to the two or more columns.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: January 23, 2024
    Inventors: Miles S. Wiscombe, Scott E. Smith, Gary L. Howe, Brian W. Huber, Tony M. Brewer
  • Patent number: 11869592
    Abstract: Apparatuses and methods for decoding addresses for memory are disclosed. An example apparatus includes a memory cell array and a row decoder. The memory cell array includes a bank of memory including a plurality of groups of memory. Each of the groups of memory includes sections of memory, and each of the sections of memory including memory cells arranged in rows and columns of memory. The row decoder decodes addresses to access a first group of memory to include rows of prime memory from a first block of memory and to include rows of prime memory from a second block of memory. The row decoder decodes the addresses to access a second group of memory to include rows of prime memory from the second block of memory and to include rows of redundant memory. The rows of redundant memory are shared with the first and second blocks of memory.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: January 9, 2024
    Inventors: Gary L. Howe, Scott E. Smith
  • Publication number: 20230307033
    Abstract: Methods, apparatuses, and systems related to operations for managing the quality of an input signal received by a device and for providing feedback in real-time. A controller can provide a reference signal to the device for the input quality check. The memory can implement the input quality check by counting the number of transitions of the reference signal for a set time period and store the resulting count value(s). The memory can use the count value(s) to determine a condition or a quality for the reference signal.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Inventors: John E. Riley, Scott E. Smith, Jennifer E. Taylor, Gary L. Howe
  • Patent number: 11755206
    Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: September 12, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Thanh K. Mai, Gary L. Howe, Daniel B. Penney
  • Patent number: 11748035
    Abstract: A memory device may include one or more memory banks that store data and one or more input buffers. The input buffers may receive command address signals to access the one or more memory banks. The memory device may operate in one of a first mode of operation or a second mode of operation. The one or more input buffers may operate under a first bias current when the memory device is in the first mode of operation or a second bias current when the memory device is in the second mode of operation, and the first bias current may be greater than the second bias current.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: September 5, 2023
    Inventor: Gary L. Howe
  • Publication number: 20230021201
    Abstract: Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.
    Type: Application
    Filed: September 7, 2022
    Publication date: January 19, 2023
    Inventors: Gary L. Howe, Miles S. Wiscombe, James S. Rehmeyer, Eric J. Stave
  • Publication number: 20220391334
    Abstract: Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.
    Type: Application
    Filed: August 6, 2022
    Publication date: December 8, 2022
    Inventors: Debra M. Bell, Vaughn N. Johnson, Kyle Alexander, Gary L. Howe, Brian T. Pecha, Miles S. Wiscombe