Abstract: A signal analyzer system is disclosed which includes an arithmetic processor containing a plurality of pipeline processor elements in parallel array with each element connected to a respective working store, with all of the elements being under microprogram control of an arithmetic element controller.A storage controller included in the system is connected to the arithmetic processor, to a system input and to a system ouput.A bulk storage included in the system is connected to the storage controller. The storage controller controls data transfers into and out of the system and between the bulk storage and arithmetic processor.A control processor included in the system is connected to the arithmetic processor and the storage controller by means of a data bus for centrally controlling the operation of the plurality of pipeline processor elements by transmitting micro control words over the bus.