Abstract: A parallel register-transfer mechanism has been disclosed above for use in the evaluation of expressions of a variable-free applicative language stored as binary directed graphs. The expression is reduced through a series of transformations until a result is obtained. A register file is provided with several crossbar networks interconnecting the various registers in the file for simultaneous transfer of their contents.

Abstract: A parallel register-transfer mechanism and control section have been disclosed above for use in a reduction process for the evaluation of expressions of a variable-free applicative language stored as binary directed graphs. The expressions are reduced through a series of transformations until a result is obtained.

Abstract: A system memory for a reduction processor which evaluates programs stored as binary graphs employing variable-free applicative language codes. These graphs are made up of nodes, each of which exists in memory and contains as its most significant bit a mark bit which when set indicates that the node is being used in a graph and when reset indicates that the node or storage location is available for future use by the processor. In order to accommodate the scanning of a number of storage locations in parallel, the system memory is divided into a node memory and the mark bit memory so that the mark bits for a number of sequential storage locations can be examined in parallel to determine which node locations are free for use by the graph manager.

Abstract: Parallel register-transfer mechanism and control section have been disclosed above for use in a reduction processor for the evaluation of expressions of a variable-free applicative language stored as binary directed graphs. The expressions are reduced through a series of transformations until a result is obtained.

Abstract: An allocator for a reduction processor which evaluates programs stored as binary graphs employing variable-free applicative language codes. These graphs are made up of nodes, each of which exists in memory and contains as its most significant bit a mark bit which when set indicates that the node is being used in a graph and when reset indicates that the node or storage location is available for future use by the processor. The allocator scans selected groups of storage locations in parallel to see if there are any unused storage locations and then places the addresses of those unused storage locations in a queue for use by the processor.

Abstract: This disclosure relates to a network of reduction processors for the evaluation of one or more functions which are stored in memory in the form of a series of nodes of a treelike graph where the nodes implement a variable-free applicative language. The respective function operators are reduced through a progressive series of transformations or substitutions until a result is obtained. During the reduction process, the processor transfers nodes to and from memory and performs various operations as required on those nodes. The processor can also create new nodes in memory and delete unused ones.

Abstract: Disclosed is a selector switch for use in forming an asynchronous network of concurrent processors where the selector switch receives a message from one input port and transmits it to one of two output ports. A path through the network which has been established can be cleared should it become apparent that that particular path has become locked in due to a malfunction of a component in one of the nodes or switches in the network.

Abstract: Disclosed is an arbiter switch for use in forming an asynchronous network of concurrent processors where the arbiter switch receives a message from one of two input ports and transmits it to its output port. A path through the network which has been established can be cleared should it become apparent that particular path has become locked in due to a malfunction of a component in one of the nodes or switches in the network.

Abstract: A four way selector switch for a five port module as a node in an asynchronous speed independent network of concurrent processors, each port of the module including an input selector switch and an output selector switch such that each selector switch has a plurality of output channels one for each of the output arbiter switches (except the arbiter switch associated with its own port). Each selector switch is adapted to select a particular output channel (arbiter switch) according to the initial bits received in the asynchronous speed independent message. In this manner, the module of the present invention can accommodate up to five simultaneous asynchronous message transmissions without nodal blocking although the average number of simultaneous messages that can be accommodated will be less.

Abstract: A five port module as a node in an asynchronous speed independent network of concurrent processors, each port of the module including an input selector switch and an output selector switch such that each selector switch has a plurality of output channels one for each of the output arbiter switches (except the arbiter switch associated with its own port). Each selector switch is adapted to select a particular output channel (arbiter switch) according to the initial bits received in the asynchronous speed independent message. In this manner, the module of the present invention can accommodate up to five simultaneous asynchronous message transmissions without nodal blocking although the average number of simultaneous messages that can be accommodated will be less. The respective arbiter and selector switches are provided with circuitry to respond to a clear signal that resets the corresponding arbiter and selector switches forming a particular transmission path should nodal blocking occur.

Abstract: A four way arbiter switch for a five port module as a node in an asynchronous speed independent network of concurrent processors, each port of the module including an input selector switch and an output selector switch such that each selector switch has a plurality of output channels one for each of the output arbiter switches (except the arbiter switch associated with its own port). Each selector switch is adapted to select a particular output channel (arbiter switch) according to the initial bits received in the asynchronous speed independent message. In this manner, the module of the present invention can accommodate up to five simultaneous asynchronous message transmissions without nodal blocking although the average number of simultaneous messages that can be accommodated will be less.

Abstract: This disclosure relates to a reduction processor for the evaluation of one or more functions which are stored in memory in the form of a series of nodes of a treelike graph where the nodes implement a variable-free applicative language. The respective function operators are reduced through a progressive series of transformations or substitutions until a result is obtained. During the reduction process, the processor transfers nodes to and from memory and performs various operations as required on those nodes. The processor can also create new nodes in memory and delete unused ones.