Patents by Inventor Gary L. Miller
Gary L. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20190370212Abstract: A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to the first connectivity circuitry by the first processor bus and configured to provide first bus transactions, to be provided to the second connectivity circuitry, to the first processor bus, the first connectivity circuitry configured to utilize a multiple simultaneous outstanding transaction capability supporting multiple simultaneous outstanding write transactions concurrent with multiple simultaneous outstanding read transactions, the second connectivity circuitry configured to provide processor bus flow control information and elasticity buffer status information pertaining to the elasticity buffer to the first connectivity circuitry via a common message for flow control.Type: ApplicationFiled: June 1, 2018Publication date: December 5, 2019Inventors: Gary L. Miller, Jeffrey Freeman, Huy Nguyen
-
Publication number: 20190370211Abstract: A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to first connectivity circuitry by a first processor bus and configured to provide first bus transactions to the first processor bus, the discrete signal lines connected to the first connectivity circuitry to provide first discrete signals indicative of discrete events, the first connectivity circuitry configured to store the first discrete signals in a plurality of virtual signal registers and to convert the first bus transactions and the first discrete signals into die-to-die message packets to be communicated to the second connectivity circuitry via a die-to-die interconnect between the first die and the second die, the first discrete signals being converted into the die-to-die message packets on a register-by-register basis.Type: ApplicationFiled: June 1, 2018Publication date: December 5, 2019Inventors: Gary L. Miller, Jeffrey Freeman
-
Patent number: 10496594Abstract: A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to the first connectivity circuitry by the first processor bus and configured to provide first bus transactions, to be provided to the second connectivity circuitry, to the first processor bus, the first connectivity circuitry configured to utilize a multiple simultaneous outstanding transaction capability supporting multiple simultaneous outstanding write transactions concurrent with multiple simultaneous outstanding read transactions, the second connectivity circuitry configured to provide processor bus flow control information and elasticity buffer status information pertaining to the elasticity buffer to the first connectivity circuitry via a common message for flow control.Type: GrantFiled: June 1, 2018Date of Patent: December 3, 2019Assignee: NXP USA, Inc.Inventors: Gary L. Miller, Jeffrey Freeman, Huy Nguyen
-
Patent number: 10496593Abstract: A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to first connectivity circuitry by a first processor bus and configured to provide first bus transactions to the first processor bus, the discrete signal lines connected to the first connectivity circuitry to provide first discrete signals indicative of discrete events, the first connectivity circuitry configured to store the first discrete signals in a plurality of virtual signal registers and to convert the first bus transactions and the first discrete signals into die-to-die message packets to be communicated to the second connectivity circuitry via a die-to-die interconnect between the first die and the second die, the first discrete signals being converted into the die-to-die message packets on a register-by-register basis.Type: GrantFiled: June 1, 2018Date of Patent: December 3, 2019Assignee: NXP USA, Inc.Inventors: Gary L. Miller, Jeffrey Freeman
-
Patent number: 10221499Abstract: A method of making a nuclear fuel structure may include reducing a metal oxide in a cathode assembly so as to deposit a metal of the metal oxide on the cathode plate of the cathode assembly, and processing the cathode plate with the metal deposited thereon to fabricate the nuclear fuel structure. The cathode plate may include an upper blade including an electrically conductive material, a lower blade portion connected to the upper blade, and a connection structure configured to secure the lower blade portion to the upper blade while providing electrical continuity. The connection structure may be configured to be disconnected from the lower blade portion to detach the lower blade portion from the upper blade.Type: GrantFiled: June 25, 2015Date of Patent: March 5, 2019Assignee: GE-Hitachi Nuclear Energy Americas LLCInventors: Gary L. Miller, Keith H. Keller
-
Patent number: 9762238Abstract: A system in a package (SIP) has a first die with a first internal voltage level, first die-to-die output circuitry, first die-to-die input circuitry, and first internal logic and a second die with a second internal voltage level, second die-to-die output circuitry, second die-to-die input circuitry, and second internal logic. A first signal is provided to the second internal logic via the first die-to-die output circuitry and the second die-to-die input circuitry, wherein each of the first die-to-die output circuitry and second die-to-die input circuitry selectively level shift the first signal based on the first and second internal voltage levels. A second signal is provided to the first internal logic via the second die-to-die output circuitry and the first die-to-die input circuitry, wherein each of the second die-to-die output circuitry and first die-to-die input circuitry selectively level shift the second signal based on the first and second internal voltage levels.Type: GrantFiled: April 3, 2017Date of Patent: September 12, 2017Assignee: NXP USA, Inc.Inventors: Gary L. Miller, Michael E. Gladden
-
Patent number: 9552279Abstract: A data bus network interface module for enabling reception and transmission of application messages to/from at least one host processing module of an integrated digital signal processing device via a data bus network is described. The data bus network interface module being arranged to receive at least one data bus message from at least one remote network node via the data bus network, read an identifier field of the received at least one data bus message, and make data content of the received at least one data bus message available to at least one debug module if the identifier field comprises an identifier value defined for debug use.Type: GrantFiled: August 16, 2013Date of Patent: January 24, 2017Assignee: NXP USA, INC.Inventors: Mark Maiolani, Ray C. Marshall, Gary L. Miller
-
Publication number: 20160376723Abstract: A method of making a nuclear fuel structure may include reducing a metal oxide in a cathode assembly so as to deposit a metal of the metal oxide on the cathode plate of the cathode assembly, and processing the cathode plate with the metal deposited thereon to fabricate the nuclear fuel structure. The cathode plate may include an upper blade including an electrically conductive material, a lower blade portion connected to the upper blade, and a connection structure configured to secure the lower blade portion to the upper blade while providing electrical continuity. The connection structure may be configured to be disconnected from the lower blade portion to detach the lower blade portion from the upper blade.Type: ApplicationFiled: June 25, 2015Publication date: December 29, 2016Applicant: GE-HITACHI NUCLEAR ENERGY AMERICAS LLCInventors: Gary L. MILLER, Keith H. KELLER
-
Patent number: 9465405Abstract: A source clock signal is received from a primary semiconductor device by a secondary semiconductor device via an interconnect. A local clock signal is generated on the secondary semiconductor device based on the source clock signal. A mode control signal is generated on the secondary semiconductor device, where the mode control signal indicates one of an unlock mode of operation and a lock mode of operation of the secondary semiconductor device. A physical interface (PHY) clock signal is generated based on the local clock signal, where the PHY clock signal includes the local clock signal during the lock mode, and the PHY clock signal includes an inverted version of the local clock signal during the unlock mode. Data received from the primary semiconductor device via the interconnect is latched at a positive edge of the PHY clock signal during the unlock mode and the lock mode.Type: GrantFiled: June 30, 2015Date of Patent: October 11, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Gary L. Miller, David D. Barrera, Michael E. Gladden
-
Patent number: 9372503Abstract: A method embodiment of the present disclosure includes receiving a delay value associated with an interconnect delay that is measured across interconnect circuitry communicatively coupling a host semiconductor device with a semiconductor device. The method also includes delaying a local clock signal by an amount of delay indicated by the delay value to produce a delayed local clock signal. The method also includes receiving a delayed source clock signal, where the delayed source clock signal is received from the host semiconductor device via the interconnect circuitry. The method also includes outputting a master clock signal based on a comparison of the delayed source clock signal and the delayed local clock signal, where the master clock signal is utilized to generate one or more aligned clock signals on the semiconductor device that are aligned with a source clock signal generated on the host semiconductor device.Type: GrantFiled: May 22, 2015Date of Patent: June 21, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Gary L. Miller, James G. Gay, Gilford E. Lubbers, Geng Zhong
-
Patent number: 9176916Abstract: Methods and systems are disclosed for address mapping between die-to-die-port (DTDP) host devices and DTDP expansion devices for combined system-in-package (SiP) solutions. Interconnect circuitry having a plurality of ports is configured to provide communication from the host device to the expansion device so that the expansion device appears to be resident on the host device. Configurable address mapping is used to re-configure the host memory map to include expansion memory map details in a seamless fashion. Further, direct circuit interconnection blocks (e.g., using copper pillar (CuP) connectors) can be used to improve connectivity and performance.Type: GrantFiled: February 25, 2013Date of Patent: November 3, 2015Assignee: Freescale Semiconductor, Inc.Inventor: Gary L. Miller
-
Patent number: 9170974Abstract: Methods and systems are disclosed for interconnecting die-to-die-port (DTDP) host devices and DTDP expansion devices for combined system-in-package (SiP) solutions. Interconnect circuitry having a plurality of ports is configured to provide communication from the host device to the expansion device so that the expansion device appears to be resident on the host device. Further, direct circuit interconnection blocks (e.g., using copper pillar (CuP) connectors) can be used to improve connectivity and performance. In addition, level shift circuitry can be utilized within expansion devices to allow for standardized interconnect signals and supply voltages to be provided by DTDP host devices to DTDP expansion devices.Type: GrantFiled: February 25, 2013Date of Patent: October 27, 2015Assignee: Freescale Semiconductor, Inc.Inventor: Gary L. Miller
-
Patent number: 9111647Abstract: A system in a package (SiP) includes a first semiconductor die having a nonvolatile memory and trim/repair circuitry, and a second semiconductor die having a volatile memory and trim/repair circuitry. The first and the second semiconductor die are in a same package. The nonvolatile memory of the first semiconductor die is configured to store trim/repair values for each of the first and the second semiconductor die. The trim/repair circuitries of the first and second semiconductor die are configured to, in response to a reset of the second semiconductor die, copy the trim/repair values from the nonvolatile memory of the first semiconductor die to the volatile memory of the second semiconductor die.Type: GrantFiled: December 19, 2013Date of Patent: August 18, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Gary L. Miller, Derek J. Beattie
-
Publication number: 20150179286Abstract: A system in a package (SiP) includes a first semiconductor die having a nonvolatile memory and trim/repair circuitry, and a second semiconductor die having a volatile memory and trim/repair circuitry. The first and the second semiconductor die are in a same package. The nonvolatile memory of the first semiconductor die is configured to store trim/repair values for each of the first and the second semiconductor die. The trim/repair circuitries of the first and second semiconductor die are configured to, in response to a reset of the second semiconductor die, copy the trim/repair values from the nonvolatile memory of the first semiconductor die to the volatile memory of the second semiconductor die.Type: ApplicationFiled: December 19, 2013Publication date: June 25, 2015Inventors: GARY L. MILLER, Derek J. Beattie
-
Patent number: 9039162Abstract: This invention relates to a media multi-feed rejection apparatus, comprising: a plurality of feed rollers; a feed roller driving means operatively connected to one of the plurality of feed rollers; a clutch means operatively connected to the other of the plurality of feed rollers; and a single channel encoder means operatively connected to the clutch means to measure a rotation of the other of the plurality of feed rollers.Type: GrantFiled: April 25, 2006Date of Patent: May 26, 2015Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Gary L. Miller, Ed Tucker, Jon Johnson
-
Patent number: 9021311Abstract: In a processing system comprising a plurality of data processors at an integrated circuit die, each data processor has a local debug module. In response to acquiring data trace information based upon a corresponding local filtering criteria, the local debug modules transmit their data trace information to a global resource from each of the local debug modules for further filtering by a common filtering criteria.Type: GrantFiled: August 28, 2012Date of Patent: April 28, 2015Assignee: Freescale Semiconductor, Inc.Inventor: Gary L. Miller
-
Publication number: 20150052405Abstract: A data bus network interface module for enabling reception and transmission of application messages to/from at least one host processing module of an integrated digital signal processing device via a data bus network is described. The data bus network interface module being arranged to receive at least one data bus message from at least one remote network node via the data bus network, read an identifier field of the received at least one data bus message, and make data content of the received at least one data bus message available to at least one debug module if the identifier field comprises an identifier value defined for debug use.Type: ApplicationFiled: August 16, 2013Publication date: February 19, 2015Inventors: Mark Maiolani, Ray C. Marshall, Gary L. Miller
-
Patent number: 8935577Abstract: In a processing system comprising a plurality of data processors at an integrated circuit die, each data processor has a local debug module. In response to acquiring data trace information based upon a corresponding local filtering criteria, the local debug modules transmit their data trace information to a global resource from each of the local debug modules for further filtering by a common filtering criteria.Type: GrantFiled: August 28, 2012Date of Patent: January 13, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Gary L. Miller, Mark Maiolani
-
Publication number: 20140244878Abstract: Methods and systems are disclosed for address mapping between die-to-die-port (DTDP) host devices and DTDP expansion devices for combined system-in-package (SiP) solutions. Interconnect circuitry having a plurality of ports is configured to provide communication from the host device to the expansion device so that the expansion device appears to be resident on the host device. Configurable address mapping is used to re-configure the host memory map to include expansion memory map details in a seamless fashion. Further, direct circuit interconnection blocks (e.g., using copper pillar (CuP) connectors) can be used to improve connectivity and performance.Type: ApplicationFiled: February 25, 2013Publication date: August 28, 2014Inventor: Gary L. Miller
-
Publication number: 20140244873Abstract: Methods and systems are disclosed for interconnecting die-to-die-port (DTDP) host devices and DTDP expansion devices for combined system-in-package (SiP) solutions. Interconnect circuitry having a plurality of ports is configured to provide communication from the host device to the expansion device so that the expansion device appears to be resident on the host device. Further, direct circuit interconnection blocks (e.g., using copper pillar (CuP) connectors) can be used to improve connectivity and performance. In addition, level shift circuitry can be utilized within expansion devices to allow for standardized interconnect signals and supply voltages to be provided by DTDP host devices to DTDP expansion devices.Type: ApplicationFiled: February 25, 2013Publication date: August 28, 2014Inventor: Gary L. Miller