Patents by Inventor Gary L. Miller

Gary L. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10529433
    Abstract: Several embodiments of memory devices and systems with offset memory component automatic calibration error recovery are disclosed herein. In one embodiment, a system includes at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to one or more of a plurality of offset read level test signals, including a base offset read level test signal. The base offset read level test signal is offset from the current read level signal by a predetermined value. The calibration circuitry is further configured to output the determined read level offset value.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni, Gary F. Besinga, Michael G. Miller, Renato C. Padilla
  • Publication number: 20190370211
    Abstract: A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to first connectivity circuitry by a first processor bus and configured to provide first bus transactions to the first processor bus, the discrete signal lines connected to the first connectivity circuitry to provide first discrete signals indicative of discrete events, the first connectivity circuitry configured to store the first discrete signals in a plurality of virtual signal registers and to convert the first bus transactions and the first discrete signals into die-to-die message packets to be communicated to the second connectivity circuitry via a die-to-die interconnect between the first die and the second die, the first discrete signals being converted into the die-to-die message packets on a register-by-register basis.
    Type: Application
    Filed: June 1, 2018
    Publication date: December 5, 2019
    Inventors: Gary L. Miller, Jeffrey Freeman
  • Publication number: 20190370212
    Abstract: A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to the first connectivity circuitry by the first processor bus and configured to provide first bus transactions, to be provided to the second connectivity circuitry, to the first processor bus, the first connectivity circuitry configured to utilize a multiple simultaneous outstanding transaction capability supporting multiple simultaneous outstanding write transactions concurrent with multiple simultaneous outstanding read transactions, the second connectivity circuitry configured to provide processor bus flow control information and elasticity buffer status information pertaining to the elasticity buffer to the first connectivity circuitry via a common message for flow control.
    Type: Application
    Filed: June 1, 2018
    Publication date: December 5, 2019
    Inventors: Gary L. Miller, Jeffrey Freeman, Huy Nguyen
  • Patent number: 10496594
    Abstract: A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to the first connectivity circuitry by the first processor bus and configured to provide first bus transactions, to be provided to the second connectivity circuitry, to the first processor bus, the first connectivity circuitry configured to utilize a multiple simultaneous outstanding transaction capability supporting multiple simultaneous outstanding write transactions concurrent with multiple simultaneous outstanding read transactions, the second connectivity circuitry configured to provide processor bus flow control information and elasticity buffer status information pertaining to the elasticity buffer to the first connectivity circuitry via a common message for flow control.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: December 3, 2019
    Assignee: NXP USA, Inc.
    Inventors: Gary L. Miller, Jeffrey Freeman, Huy Nguyen
  • Patent number: 10496593
    Abstract: A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to first connectivity circuitry by a first processor bus and configured to provide first bus transactions to the first processor bus, the discrete signal lines connected to the first connectivity circuitry to provide first discrete signals indicative of discrete events, the first connectivity circuitry configured to store the first discrete signals in a plurality of virtual signal registers and to convert the first bus transactions and the first discrete signals into die-to-die message packets to be communicated to the second connectivity circuitry via a die-to-die interconnect between the first die and the second die, the first discrete signals being converted into the die-to-die message packets on a register-by-register basis.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: December 3, 2019
    Assignee: NXP USA, Inc.
    Inventors: Gary L. Miller, Jeffrey Freeman
  • Publication number: 20190320686
    Abstract: A method of making a gel-type livestock feed includes initially forming a feed mixture by mixing feed nutrient components, water, alginate, and a calcium component insoluble in water or a sequestrate to inhibit the calcium component from reacting with the alginate. Once the feed mixture is formed, the calcium component is solubilized or the sequestrates affecting the reactivity between the alginate and the calcium component is removed such that a gel feed is formed that includes a gel matrix containing the feed nutrient components. The gel feed may then be fed to the livestock. In another aspect of the present invention, piglets are weaned by feeding the gel feed for at least seven days directly after weaning. The gel feed may also include protein derived from blood with or without egg protein.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Inventors: Kent Lanter, Brenda de Rodas, Bill L. Miller, Gary E. Fitzner
  • Publication number: 20190260979
    Abstract: This disclosure pertains to operations, systems, and computer readable media to capture images of a scene using a camera array and process the captured images based on a viewer's point of view (POV) for immersive augmented reality, live display wall, head mounted display, video conferencing, and similar applications. In one implementation, the disclosed subject matter provides a complete view to a viewer by combining images captured by a camera array. In another implementation, the disclosed subject matter tracks the viewer's POV as he moves from one location to another and displays images in accordance with his varying POV. The change of the viewer's POV is inclusive of movements in the X, Y, and Z dimensions.
    Type: Application
    Filed: January 7, 2019
    Publication date: August 22, 2019
    Inventors: Ricardo J. Motta, Gary L. Vondran, JR., Manohar B. Srikanth, Brett D. Miller
  • Patent number: 10383346
    Abstract: A method of making a gel-type livestock feed includes initially forming a feed mixture by mixing feed nutrient components, water, alginate, and a calcium component insoluble in water or a sequestrate to inhibit the calcium component from reacting with the alginate. Once the feed mixture is formed, the calcium component is solubilized or the sequestrates affecting the reactivity between the alginate and the calcium component is removed such that a gel feed is formed that includes a gel matrix containing the feed nutrient components. The gel feed may then be fed to the livestock. In another aspect of the present invention, piglets are weaned by feeding the gel feed for at least seven days directly after weaning. The gel feed may also include protein derived from blood with or without egg protein.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: August 20, 2019
    Assignee: Purina Mills, LLC
    Inventors: Kent Lanter, Brenda de Rodas, Bill L. Miller, Gary E. Fitzner
  • Publication number: 20190200062
    Abstract: Methods and apparatus for providing protected content to subscribers of a managed (e.g., MSO) network via a content source accessible via an internetwork such as the Internet. In one embodiment, a user accesses a programmer website website, and requests content. The programmer determines whether the requesting user is permitted to access the content, and what rights or restrictions are associated with the user. This includes authenticating the user as a subscriber of the MSO, and determining the subscriber's subscription level. In another embodiment, a user's account with the MSO and programmer may be federated, thus a given user will have MSO-specific information regarding its identity (such as login information, GUID, etc.) and/or information regarding subscription level and service details, stored at the programmer. Messages received from the MSO representing permission for the user to access content may also be stored at the programmer site for later reference.
    Type: Application
    Filed: November 19, 2018
    Publication date: June 27, 2019
    Inventors: Gary Cronk, Jonathan Putsch, James Boutilier, Paul L. Miller, Michael Dillon
  • Publication number: 20190150480
    Abstract: A method of making a gel-type livestock feed includes initially forming a feed mixture by mixing feed nutrient components, water, alginate, and a calcium component insoluble in water or a sequestrate to inhibit the calcium component from reacting with the alginate. Once the feed mixture is formed, the calcium component is solubilized or the sequestrates affecting the reactivity between the alginate and the calcium component is removed such that a gel feed is formed that includes a gel matrix containing the feed nutrient components. The gel feed may then be fed to the livestock. In another aspect of the present invention, piglets are weaned by feeding the gel feed for at least seven days directly after weaning. The gel feed may also include protein derived from blood with or without egg protein.
    Type: Application
    Filed: January 23, 2019
    Publication date: May 23, 2019
    Inventors: Kent Lanter, Brenda de Rodas, Bill L. Miller, Gary E. Fitzner
  • Patent number: 10221499
    Abstract: A method of making a nuclear fuel structure may include reducing a metal oxide in a cathode assembly so as to deposit a metal of the metal oxide on the cathode plate of the cathode assembly, and processing the cathode plate with the metal deposited thereon to fabricate the nuclear fuel structure. The cathode plate may include an upper blade including an electrically conductive material, a lower blade portion connected to the upper blade, and a connection structure configured to secure the lower blade portion to the upper blade while providing electrical continuity. The connection structure may be configured to be disconnected from the lower blade portion to detach the lower blade portion from the upper blade.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: March 5, 2019
    Assignee: GE-Hitachi Nuclear Energy Americas LLC
    Inventors: Gary L. Miller, Keith H. Keller
  • Patent number: 9762238
    Abstract: A system in a package (SIP) has a first die with a first internal voltage level, first die-to-die output circuitry, first die-to-die input circuitry, and first internal logic and a second die with a second internal voltage level, second die-to-die output circuitry, second die-to-die input circuitry, and second internal logic. A first signal is provided to the second internal logic via the first die-to-die output circuitry and the second die-to-die input circuitry, wherein each of the first die-to-die output circuitry and second die-to-die input circuitry selectively level shift the first signal based on the first and second internal voltage levels. A second signal is provided to the first internal logic via the second die-to-die output circuitry and the first die-to-die input circuitry, wherein each of the second die-to-die output circuitry and first die-to-die input circuitry selectively level shift the second signal based on the first and second internal voltage levels.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: September 12, 2017
    Assignee: NXP USA, Inc.
    Inventors: Gary L. Miller, Michael E. Gladden
  • Patent number: 9552279
    Abstract: A data bus network interface module for enabling reception and transmission of application messages to/from at least one host processing module of an integrated digital signal processing device via a data bus network is described. The data bus network interface module being arranged to receive at least one data bus message from at least one remote network node via the data bus network, read an identifier field of the received at least one data bus message, and make data content of the received at least one data bus message available to at least one debug module if the identifier field comprises an identifier value defined for debug use.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: January 24, 2017
    Assignee: NXP USA, INC.
    Inventors: Mark Maiolani, Ray C. Marshall, Gary L. Miller
  • Publication number: 20160376723
    Abstract: A method of making a nuclear fuel structure may include reducing a metal oxide in a cathode assembly so as to deposit a metal of the metal oxide on the cathode plate of the cathode assembly, and processing the cathode plate with the metal deposited thereon to fabricate the nuclear fuel structure. The cathode plate may include an upper blade including an electrically conductive material, a lower blade portion connected to the upper blade, and a connection structure configured to secure the lower blade portion to the upper blade while providing electrical continuity. The connection structure may be configured to be disconnected from the lower blade portion to detach the lower blade portion from the upper blade.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Applicant: GE-HITACHI NUCLEAR ENERGY AMERICAS LLC
    Inventors: Gary L. MILLER, Keith H. KELLER
  • Patent number: 9465405
    Abstract: A source clock signal is received from a primary semiconductor device by a secondary semiconductor device via an interconnect. A local clock signal is generated on the secondary semiconductor device based on the source clock signal. A mode control signal is generated on the secondary semiconductor device, where the mode control signal indicates one of an unlock mode of operation and a lock mode of operation of the secondary semiconductor device. A physical interface (PHY) clock signal is generated based on the local clock signal, where the PHY clock signal includes the local clock signal during the lock mode, and the PHY clock signal includes an inverted version of the local clock signal during the unlock mode. Data received from the primary semiconductor device via the interconnect is latched at a positive edge of the PHY clock signal during the unlock mode and the lock mode.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: October 11, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gary L. Miller, David D. Barrera, Michael E. Gladden
  • Patent number: 9372503
    Abstract: A method embodiment of the present disclosure includes receiving a delay value associated with an interconnect delay that is measured across interconnect circuitry communicatively coupling a host semiconductor device with a semiconductor device. The method also includes delaying a local clock signal by an amount of delay indicated by the delay value to produce a delayed local clock signal. The method also includes receiving a delayed source clock signal, where the delayed source clock signal is received from the host semiconductor device via the interconnect circuitry. The method also includes outputting a master clock signal based on a comparison of the delayed source clock signal and the delayed local clock signal, where the master clock signal is utilized to generate one or more aligned clock signals on the semiconductor device that are aligned with a source clock signal generated on the host semiconductor device.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: June 21, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gary L. Miller, James G. Gay, Gilford E. Lubbers, Geng Zhong
  • Patent number: 9176916
    Abstract: Methods and systems are disclosed for address mapping between die-to-die-port (DTDP) host devices and DTDP expansion devices for combined system-in-package (SiP) solutions. Interconnect circuitry having a plurality of ports is configured to provide communication from the host device to the expansion device so that the expansion device appears to be resident on the host device. Configurable address mapping is used to re-configure the host memory map to include expansion memory map details in a seamless fashion. Further, direct circuit interconnection blocks (e.g., using copper pillar (CuP) connectors) can be used to improve connectivity and performance.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: November 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Gary L. Miller
  • Patent number: 9170974
    Abstract: Methods and systems are disclosed for interconnecting die-to-die-port (DTDP) host devices and DTDP expansion devices for combined system-in-package (SiP) solutions. Interconnect circuitry having a plurality of ports is configured to provide communication from the host device to the expansion device so that the expansion device appears to be resident on the host device. Further, direct circuit interconnection blocks (e.g., using copper pillar (CuP) connectors) can be used to improve connectivity and performance. In addition, level shift circuitry can be utilized within expansion devices to allow for standardized interconnect signals and supply voltages to be provided by DTDP host devices to DTDP expansion devices.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: October 27, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Gary L. Miller
  • Patent number: 9111647
    Abstract: A system in a package (SiP) includes a first semiconductor die having a nonvolatile memory and trim/repair circuitry, and a second semiconductor die having a volatile memory and trim/repair circuitry. The first and the second semiconductor die are in a same package. The nonvolatile memory of the first semiconductor die is configured to store trim/repair values for each of the first and the second semiconductor die. The trim/repair circuitries of the first and second semiconductor die are configured to, in response to a reset of the second semiconductor die, copy the trim/repair values from the nonvolatile memory of the first semiconductor die to the volatile memory of the second semiconductor die.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: August 18, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Gary L. Miller, Derek J. Beattie
  • Publication number: 20150179286
    Abstract: A system in a package (SiP) includes a first semiconductor die having a nonvolatile memory and trim/repair circuitry, and a second semiconductor die having a volatile memory and trim/repair circuitry. The first and the second semiconductor die are in a same package. The nonvolatile memory of the first semiconductor die is configured to store trim/repair values for each of the first and the second semiconductor die. The trim/repair circuitries of the first and second semiconductor die are configured to, in response to a reset of the second semiconductor die, copy the trim/repair values from the nonvolatile memory of the first semiconductor die to the volatile memory of the second semiconductor die.
    Type: Application
    Filed: December 19, 2013
    Publication date: June 25, 2015
    Inventors: GARY L. MILLER, Derek J. Beattie