Patents by Inventor Gary L. Milo
Gary L. Milo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10056306Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.Type: GrantFiled: February 4, 2016Date of Patent: August 21, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Edward C. Cooney, III, Gary L. Milo, Thomas W. Weeks, Patrick S. Spinney, John C. Hall, Brian P. Conchieri, Brett T. Cucci, Thomas C. Lee
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Patent number: 9825119Abstract: Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.Type: GrantFiled: August 2, 2016Date of Patent: November 21, 2017Assignee: International Business Machines CorporationInventors: Max G. Levy, Gary L. Milo, David C. Thomas
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Patent number: 9825120Abstract: Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.Type: GrantFiled: August 2, 2016Date of Patent: November 21, 2017Assignee: International Business Machines CorporationInventors: Max G. Levy, Gary L. Milo, David C. Thomas
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Publication number: 20170229358Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.Type: ApplicationFiled: February 4, 2016Publication date: August 10, 2017Inventors: Edward C. Cooney, III, Gary L. Milo, Thomas W. Weeks, Patrick S. Spinney, John C. Hall, Brian P. Conchieri, Brett T. Cucci, Thomas C. Lee
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Patent number: 9577023Abstract: A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.Type: GrantFiled: June 4, 2013Date of Patent: February 21, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Edward C. Cooney, III, Dinh Dang, David A. DeMuynck, Sarah A. McTaggart, Gary L. Milo, Melissa J. Roma, Jeffrey L. Thompson, Thomas W. Weeks
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Patent number: 9548349Abstract: Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.Type: GrantFiled: June 25, 2014Date of Patent: January 17, 2017Assignee: International Business Machines CorporationInventors: Max G. Levy, Gary L. Milo, David C. Thomas
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Publication number: 20160343798Abstract: Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.Type: ApplicationFiled: August 2, 2016Publication date: November 24, 2016Inventors: Max G. Levy, Gary L. Milo, David C. Thomas
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Publication number: 20160343797Abstract: Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.Type: ApplicationFiled: August 2, 2016Publication date: November 24, 2016Inventors: Max G. Levy, Gary L. Milo, David C. Thomas
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Patent number: 9484301Abstract: Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.Type: GrantFiled: May 21, 2015Date of Patent: November 1, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Max G. Levy, Gary L. Milo, Matthew D. Moon, Anthony C. Speranza, Timothy D. Sullivan, David C. Thomas, Steven S. Williams
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Patent number: 9435948Abstract: Various embodiments include a silicon-based optical waveguide structure locally on a bulk silicon substrate, and systems and program products for forming such a structure by modifying an integrated circuit (IC) design structure. Embodiments include implementing processes of preparing manufacturing data for formation of the IC design structure in a computer-implemented IC formation system, wherein the preparing of the manufacturing data includes inserting instructions into the manufacturing data to convert an edge of the at least one shape from a <110> crystallographic direction to a <100> crystallographic direction.Type: GrantFiled: June 13, 2014Date of Patent: September 6, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Robert K. Leidy, Mark D. Levy, Qizhi Liu, Gary L. Milo, Steven M. Shank
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Patent number: 9231089Abstract: Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench. Due to the different contours of the sidewalls and, thereby the different crystal orientations, one sidewall etches faster than the other, resulting in an asymmetric trench. Also disclosed is a bipolar semiconductor device formation method that incorporates the above-mentioned trench formation technique when forming a trench isolation region that undercuts an extrinsic base region and surrounds a collector pedestal.Type: GrantFiled: April 23, 2015Date of Patent: January 5, 2016Assignee: International Business Machines CorporationInventors: Robert K. Leidy, Mark D. Levy, Qizhi Liu, Gary L. Milo
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Publication number: 20150380478Abstract: Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.Type: ApplicationFiled: June 25, 2014Publication date: December 31, 2015Inventors: Max G. Levy, Gary L. Milo, David C. Thomas
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Publication number: 20150363535Abstract: Various embodiments include a silicon-based optical waveguide structure locally on a bulk silicon substrate, and systems and program products for forming such a structure by modifying an integrated circuit (IC) design structure. Embodiments include implementing processes of preparing manufacturing data for formation of the IC design structure in a computer-implemented IC formation system, wherein the preparing of the manufacturing data includes inserting instructions into the manufacturing data to convert an edge of the at least one shape from a <110> crystallographic direction to a <100> crystallographic direction.Type: ApplicationFiled: June 13, 2014Publication date: December 17, 2015Inventors: Robert K. Leidy, Mark D. Levy, Qizhi Liu, Gary L. Milo, Steven M. Shank
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Patent number: 9196592Abstract: Various embodiments include managing metal densities in kerf sections of an integrated circuit (IC) wafer. In some embodiments, a method includes: forming an integrated circuit (IC) wafer including a wafer kerf region, the wafer kerf region having a metal density of less than approximately 0.5 percent relative to a total density of the wafer kerf region.Type: GrantFiled: January 10, 2014Date of Patent: November 24, 2015Assignee: International Business Machines CorporationInventors: Edward C. Cooney, III, Jeffrey P. Gambino, Richard S. Graf, Gary L. Milo
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Publication number: 20150255395Abstract: Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.Type: ApplicationFiled: May 21, 2015Publication date: September 10, 2015Inventors: Max G. Levy, Gary L. Milo, Matthew D. Moon, Anthony C. Speranza, Timothy D. Sullivan, David C. Thomas, Steven S. Williams
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Publication number: 20150228769Abstract: Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench. Due to the different contours of the sidewalls and, thereby the different crystal orientations, one sidewall etches faster than the other, resulting in an asymmetric trench. Also disclosed is a bipolar semiconductor device formation method that incorporates the above-mentioned trench formation technique when forming a trench isolation region that undercuts an extrinsic base region and surrounds a collector pedestal.Type: ApplicationFiled: April 23, 2015Publication date: August 13, 2015Inventors: Robert K. Leidy, Mark D. Levy, Qizhi Liu, Gary L. Milo
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Publication number: 20150200167Abstract: Various embodiments include managing metal densities in kerf sections of an integrated circuit (IC) wafer. In some embodiments, a method includes: forming an integrated circuit (IC) wafer including a wafer kerf region, the wafer kerf region having a metal density of less than approximately 0.5 percent relative to a total density of the wafer kerf region.Type: ApplicationFiled: January 10, 2014Publication date: July 16, 2015Applicant: International Business Machines CorporationInventors: Edward C. Cooney, III, Jeffrey P. Gambino, Richard S. Graf, Gary L. Milo
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Patent number: 9059233Abstract: Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench. Due to the different contours of the sidewalls and, thereby the different crystal orientations, one sidewall etches faster than the other, resulting in an asymmetric trench. Also disclosed is a bipolar semiconductor device formation method that incorporates the above-mentioned trench formation technique when forming a trench isolation region that undercuts an extrinsic base region and surrounds a collector pedestal.Type: GrantFiled: November 19, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Robert K. Leidy, Mark D. Levy, Qizhi Liu, Gary L. Milo
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Patent number: 9059258Abstract: Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.Type: GrantFiled: March 4, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Max G. Levy, Gary L. Milo, Matthew D. Moon, Anthony C. Speranza, Timothy D. Sullivan, David C. Thomas, Steven S. Williams
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Publication number: 20150137186Abstract: Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench. Due to the different contours of the sidewalls and, thereby the different crystal orientations, one sidewall etches faster than the other, resulting in an asymmetric trench. Also disclosed is a bipolar semiconductor device formation method that incorporates the above-mentioned trench formation technique when forming a trench isolation region that undercuts an extrinsic base region and surrounds a collector pedestal.Type: ApplicationFiled: November 19, 2013Publication date: May 21, 2015Applicant: International Business Machines CorporationInventors: Robert K. Leidy, Mark D. Levy, Qizhi Liu, Gary L. Milo