Patents by Inventor Gary L. Small

Gary L. Small has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5563509
    Abstract: An adapter unit configurable for testing ICs having different power and ground contact configurations is customized for one of such configuration and mounted on a load board having first and second plurality of signal contacts, wherein respective pairs of the first and second plurality of signal contacts are connected to both a contact of the IC and a test channel from an IC tester. The adapter unit is mounted on the load board making contact with the first plurality of signal contacts, while a DUT board holding the IC is mounted on the load board making contact with the second plurality of signal contacts. The adapter unit includes a plurality of signal contacts respectively connected to the first plurality of signal contacts of the load board, a power bus ring connected to a power line provided by the IC tester, and a ground bus ring connected to a ground line from the IC tester.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: October 8, 1996
    Assignee: VLSI Technology, Inc.
    Inventor: Gary L. Small
  • Patent number: 5491426
    Abstract: An adaptable probe card assembly for testing an IC die includes a probe card and a decoupling apparatus selectably mounted on the probe card. A different decoupling apparatus is used for each IC die to be tested having a different power and ground bond pad configuration. Each decoupling apparatus includes a conductive ground bus connected to ground, a nonconductive support structure, and a plurality of chip capacitors sandwiched between the conductive ground bus and nonconductive support structure in such positions that they are each connected at one end to the ground bus and at another end to one of the power or ground bond pads of the IC die being tested via a conductive contact extending through a hole in the nonconductive support structure down to a signal contact formed on the probe card, which signal contact is in turn, connected to a needle making touch contact with the appropriate power or ground bond pad of the IC die being tested.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: February 13, 1996
    Assignee: VLSI Technology, Inc.
    Inventor: Gary L. Small
  • Patent number: 5110628
    Abstract: A method and apparatus for marking or erasing a marking on a semiconductor chip package having leads. The apparatus comprises a circular disk has many pockets on one surface near its circumference suitable for holding semiconductor chips. Each pocket has a pedestal rising from the bottom of the pocket and suitable for supporting the bottom portion of a semiconductor chip package. The edges of the pocket and the pedestal define between them space suitable for housing the leads of the package. The pedestal has a hole therein which can be evacuated so that the package is held to the pedestal by atmospheric pressure so that the top surface of the package may be marked or in marking thereon can be erased. Thus the package is held to the pedestal by sufficient force for the marking or erasing process. The leads of the package are therefore not bent or otherwise disturbed. Rotation of the disk allows the packages to be sequentially marked or erased.
    Type: Grant
    Filed: March 15, 1990
    Date of Patent: May 5, 1992
    Assignee: VLSI Technology, Inc.
    Inventors: David L. Ganapol, Gary L. Small