Abstract: The present invention uses a logic control to determine which of a plurality of processors receives priority, and generates WAIT signals for the non-selected processor. Further, user configurable pins exist that allow the user to determine the priority that the attached processor will obtain when simultaneous chip selects are transmitted.

Abstract: The present invention provides a controller that operates using two different processors. Each processor performs certain predetermined functions. A control processor is responsible for switching AC power distribution and control, while a message processor is responsible for messaging. A polling scheme and arbitration logic prevent data transfers relating to these two processors from interfering with each other. A configurable interface allows many different types of appliances to attach to the system, and a serial multimode interface further enhances the configurability of the system.

Abstract: A electrical transmission line termination device capable of performing various termination requirements including matching the line impedance of wires in a transmission line with load impedances, electrically connecting conductors in a transmission line for maintaining electrical continuity, detecting improper wiring of the various wires in a transmission line, and connecting a cable shielding conductor to a ground wire.

Abstract: Apparatus whereby data processing units exchange information with each other through a common memory without delay caused by limiting access to the memory to one data processing unit at a time.The invention includes a pair of random access memories (RAMS); a first logic circuit controlled by one of the data processing units (DPU) and the address signals from both DPUs; first and second sets of gates controlled by the first logic circuit to allow one DPU access to one RAM while the other DPU has access to the other RAM; and a second logic circuit (or "handshake" circuitry) to coordinate operation of the DPUs so that each DPU has read/write access to one or the other of the RAMs at all times. In operation, one DPU has access to one RAM while the other DPU has access to the other RAM. At the appropriate time, as determined by the handshake logic circuitry, the DPU access is switched between RAMs.

Abstract: A protection and fault detection circuit for an electrically isolated semiconductor power driver acting as a switch to connect a load such as a relay coil to a source of voltage employs logic circuitry responsive to input signals indicative, respectively, of the desired state of driver operation and the conductive condition of the driver itself to effect a rendering of the device to the nonconducting state when an overload or other fault condition exists. A monitoring circuit responsive to specified operating parameters of the semiconductor power driver and its associated circuitry provides an output fault signal which is indicative of a fault condition and may be employed for remedial and/or indicating purposes.