Abstract: A GPS receiver and an RF GPS integrated circuit for receiving a GPS signal. The GPS integrated circuit includes a synthesizer for generating LO signals, first and second downconverters for using the LO signals for downconverting the GPS signal, and a sampler for providing in-phase and quadrature phase sampled output signals representative of the GPS signal. The synthesizer includes a multi-mode divider for providing substantially the same first LO frequency at about the midpoint of the L1 and L2 GPS lo frequencies for either of two reference frequencies. The RF GPS integrated circuit uses an entirely on-chip voltage controlled oscillator (VCO) having a resonator for generating the LO signals and an entirely on-chip filter for filtering a first intermediate frequency signal.

Abstract: A jamming signal cancellation method and apparatus for removing an undesired in-band CW jamming signal from a desired spread spectrum signal. The jamming cancellation apparatus includes a limiter, a summer, and a feedback loop. The feedback loop includes the summer, a harmonic filter, a mixer, a loop/filter amplifier, and an adjustable gain control (AGC). The limiter limits the waveform of the input signal and issues a limited signal to the AGC and the mixer. The AGC controls the amplitude of the limited signal and passes a controlled amplitude signal to the summer. The summer takes a difference between the input signal and the controlled amplitude signal and passes a difference signal to the filter. The filter filters the harmonics that were created by the limiter and passes an output signal to the mixer. The mixer multiplies the filtered signal by the limited signal to provide an error signal that is proportional to the amplitude of the fundamental frequency in the difference signal.

Abstract: A frequency synthesizer comprises a voltage controlled oscillator (VCO) with an output frequency f.sub.out that is dependent on a VCO-control voltage input. A divide-by-k counter is connected to receive the output frequency f.sub.out and to output a pair of in-phase and quadrature phase signals f.sub.k. A vector modulator is connected to receive the in-phase and quadrature phase signals f.sub.k and the output frequency f.sub.out, and outputs a single sideband (SSB) modulated output f.sub.n comprising only one of the sum (f.sub.out +f.sub.k) or difference (f.sub.out -f.sub.k) products. A divide-by-n counter is connected to receive the modulated output f.sub.n and to output a feedback frequency sample f.sub.f. And a phase detector is connected to receive the feedback frequency sample f.sub.f and to compare it with a reference frequency f.sub.r. A phase error output signal is provided for the VCO-control voltage input.

Abstract: A GPS receiver downconverter combines on a single integrated circuit, a first super-heterodyne mixer, a voltage controlled oscillator, a phase locked loop, a pair of quadrature mixers and a pair of quantizers with in-phase and quadrature-phase sampler outputs operable at twenty-five MHz and 2.5 MHz. Emitter-coupled logic and special low-voltage bipolar semiconductor technology are combined for 3.3 volt operation at under one hundred milliwatts.

Abstract: A system for processing inphase and quadrature data channels, such as a Costas loop QPSK demodulator, employs an additional feedback loop for adjustment of phase offset between carrier reference signals, this loop being in addition to the Costas error loop for control of frequency and phase of an oscillator which provides the regenerated carrier signal. The additional loop employs cross-channel products of demodulated inphase and quadrature data signals as does the Costas loop. The regenerated carrier is applied via an adjustable phase-offset unit to provide quadrature carrier reference signals to phase detectors of inphase and quadrature data channels. The phase offset unit includes a 90 degree hybrid circuit energized by the carrier signal at a main input port plus an adjustable fraction of the carrier power applied to an auxiliary input port.

Abstract: An embodiment of the present invention combines, on a single integrated circuit, a first bipolar transistor in a common-emitter configuration capacitively coupled to a second bipolar transistor in a common-base configuration, together with a capacitive input coupling for a single-ended input and directly-coupled collector outputs for a differential-output for driving successive differential-input and differential-output emitter-coupled transistor pairs for multiple stages of amplifier gain.

Abstract: An embodiment of the present invention is a single-chip GPS receiver front-end comprising a radio frequency amplifier, a voltage-controlled oscillator operating at a first local oscillator frequency, a divide by seven and one-half counter for deriving a second local oscillator frequency from the first and a first and second mixer. The local oscillator frequency is mid-way between two carrier frequencies of interest that may be received by the radio frequency amplifier and the first mixer produces a first intermediate frequency. The second local oscillator frequency is then beat with the first intermediate frequency in the second mixer to produce a second intermediate frequency. A dual-conversion super heterodyne configuration is therefore employed in which the first and second local oscillator frequencies are derived from a single oscillator and the first local oscillator frequency is seven and one-half times the second local oscillator frequency.

Abstract: An embodiment of the present invention is a voltage controlled oscillator (VCO) comprised of a differential pair of transistors that have respective positive feedback paths with phase-lead networks cross-coupled. Each positive feedback path on each side has two different phase-lead branches. The two phase-lead branches have the same phase differences on each side of the differential pair, in order to maintain a symmetry that improves common-mode noise rejection on a voltage control differential input. Current-steering is used to control the mixture of currents that arrive at the bases of the differential transistor pair from the respective two different phase-lead branches, and thereby changing the frequency of the VCO.

Abstract: An electronic data filter system (10), which functions as an approximation of a perfect matched filter, receives a conventional square-wave digital input signal (12) and outputs a filtered output signal (18). Output signal (18) appears as the summed integral of input signal (12). Filter system (10) includes a rate detector (50), which receives input signal (12) and provides a tuning voltage (16), and a data filter (30) which provides output signal (18). Data filter (30) includes, arranged in series, a notch filter (80) and a low-pass filter (90), wherein such filters (80, 90) contain capacitive-inductive circuits having certain value ratios which are tunable responsive to tuning voltage (16). Signal degradation of the filtered signal (12, 18) is minimized by filter system (10), which reduces the bit error rate (BER) and noise bandwidth of the filtered signal (12, 18). In one embodiment, data filters (30) are cascaded in parallel to extend data filtering bandwidth.

Abstract: A lock detector (12) used in conjunction with a bit synchronizer (14) for determining when a random binary input signal (2) is in lock with a clock (7) generated by the bit synchronizer (14). A window comparator (3, 5; or 23, 25, 27) determines whether the amplitude of the input signal (2) is within or without an amplitude window, and generates a signal (33) as a result of said determination. This signal (33) is sampled at periodic sampling points (X, Y). The set of X sampling points and set of Y sampling points are interleaved and usually separated by half a bit period. The X samples and Y samples are averaged and compared. Means (19) are provided for declaring a lock condition when the X average exceeds the Y average by a preselected threshold (V.sub.REF), which occurs when the X points are positioned near mid-points of data bits (35) and the Y points are positioned near data transitions (39). The circuit (12) will not lock on false sidebands and can operate at very low signal-to-noise ratios.

Abstract: A current balanced linear amplifier which does not contain a transformer. A differential transistor pair (22, 32) forms the amplifying element, with at least one transistor (22 or 32) having an input signal (71, 72) applied to its base. A current sink (52) sinking a fixed value of current (I) is coupled to the commonly-coupled emitters of the transistor pair (22, 32). Coupled to the collector of each amplifying transistor (22, 32) is a self-biasing constant current source (2, 12) which produces a fixed amount of current (I/2) equal to one half the current (I) sunk by the current sink (52). Each self-biasing constant current source (2, 12) comprises a field effect transistor (2, 12) having a capacitor (6, 16) connected between the gate G and source S of the FET (2, 12) in a positive feedback arrangement. The balanced current output (61, 62) is taken from the collectors of each of the two amplifying transistors (22, 32).

Abstract: A dynamic electronic switch (10) having n inputs (2) and m outputs (4), where n and m are any positive integers. The electromagnetic signal on any given input (2) may be switched onto any number of outputs (4), but any given output (4) may have no more than one input signal switched thereonto at any given time. Switching nodes (8), comprising at least one switching diode (11, 13, 15) and a directional edge coupler (17) embedded between two parallel ground planes (9, 1) in a planar mother board (5), perform switching at each intersection of an input (2) and an output (4). Each output (4) is mounted on a planar dielectric summer board (6) positioned orthogonal to the mother board (5).

Abstract: An amplifier is disclosed which is capable of operation from 0 MHz to over 100 MHz with very low distortion over this entire range. Several inputs may be combined without affecting the gain of the amplifier. Several outputs may be combined without adding to the distortion products significantly. A pair of common-base symmetrically juxtaposed transistors drives a pair of symmetrical common-emitter transistors. An AC and DC feedback loop is provided along the line of symmetry. In addition, each symmetrical half of the set of four transistors has a DC feedback loop which balances current between stages of said half and inhibits overcurrent conditions in the transistors of that half.

Abstract: A high bandwidth transversal filter is described having an input impedance matching network, a tapped delay line, a plurality of weighting amplifiers, a distributed summing circuit, and an output impedance matching network. The delay line is implemented with a transmission line. The input impedance of this transversal filter depends on the inductance and capacitance of the transmission line and the capacitance of the inputs of each of the FET's used as weighting amplifiers. The gates of the FET's provide high impedance low loss taps of the delay line. The weighting is accomplished by either varying the drain current of the FET's or by using capacitive voltage dividers to apportion the tapped signals. The resulting weighted signals are applied to a distributed summing circuit which provides both high bandwidth summing and additional delays. This summer is also implemented with a tapped transmission line.

Abstract: This on-line circuit estimates the bit error rate (BER) of a binary data signal stream in the presence of noise uncorrelated with the signal. For a binary data signal having two states, e.g., plus V and minus V biased around a specified reference level (REF), the circuit counts the number of instances in which the received signal deviates more than 2V from the reference level. This accumulated count gives an accurate estimate of the BER over several orders of magnitude variation of the BER. One embodiment counts just the deviations in a positive direction. This circuit functions independently of any bit pattern and can be used for on-line monitoring without decreasing the information carrying capability of the link. The time required to accumulate a statistically significant sample is the same as for a direct comparison between sent and received bits.

Abstract: A rubble and core removal apparatus including a casing, open at one end, with spirally extending flighting disposed therein, the flighting being secured to the inner wall of the casing and extending radially inwardly thereof in changing dimension, the casing having a connection to permit rotation and lifting of the apparatus.

Abstract: An improved drill rig having an auger and casing driver assembly, in combination, wherein a weight assembly is provided in combination with the drill rig assembly to be sequentially impacted upon a casing to be driven simultaneously with operation of the auger which is defining the well hole so that a casing is inserted into the well hole at the same time the well hole is being defined.

Abstract: A bottle carrier case comprises a wall part and a bottle support tray part of moistureproof material fixedly attached together. The wall part is formed of multi-wall panels, and the tray part has upstanding flanges along its edges secured to the wall part between the wall panels. Ledges on the tray part engage lower edges of wall part panels to prevent contact of such edges upon a support surface on which the tray part may be supported thus preventing wicking of moisture on such surface through the wall edges which are preferably of paperboard. Bottle support platforms extend from the top surface of the tray part upon which bottles are supported, leaving shallow recess thereunder to accommodate the tops of bottles, thus permitting cross stacking of cases. Reinforcing ribs are provided about each support platform; and suitable drainage passages and openings are also provided for escape of liquids.

Abstract: A bottle carrier case comprises a wall part and a bottle support tray part of moistureproof material fixedly attached together. The wall part is formed of multi-wall panels, and the tray part has upstanding flanges along its edges secured to the wall part between the wall panels. Ledges on the tray part engage lower edges of wall part panels to prevent contact of such edges upon a support surface on which the tray part may be supported thus preventing wicking of moisture on such surface through the wall edges which are preferably of paperboard. Bottle support platforms extend from the top surface of the tray part upon which bottles are supported, leaving shallow recess thereunder to accommodate the tops of bottles, thus permitting cross stacking of cases. Reinforcing ribs are provided about each support platform; and suitable drainage passages and openings are also provided for escape of liquids.