Patents by Inventor Gary Liu

Gary Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260073949
    Abstract: A data storage device may include a sealed inner enclosure, wherein a gaseous environment inside of the sealed inner enclosure differs from a standard air environment; an outer cover situated over and coupled to at least a portion of the sealed inner enclosure; and an environment-controlling substance situated between the sealed inner enclosure and the outer cover. The sealed inner enclosure comprises at least one membrane to allow the environment-controlling substance to affect the gaseous environment inside of the sealed inner enclosure. A method of manufacturing a data storage device may comprise sealing an inner enclosure of the data storage device; applying an outer cover to the data storage device; including an environment-controlling substance between the inner enclosure and the outer cover; and creating a non-standard air environment within the inner enclosure of the data storage device.
    Type: Application
    Filed: September 10, 2024
    Publication date: March 12, 2026
    Applicant: Western Digital Technologies, Inc.
    Inventors: Dongying LI, Miki NAMIHISA, Gary LIU, Henry Chi Hang YIP, Yixiang ZHANG, Shin NAGAHIRO, David DUDEK, Sukumar RAJAURIA, Qing DAI
  • Publication number: 20250357195
    Abstract: A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.
    Type: Application
    Filed: July 30, 2025
    Publication date: November 20, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Cherng-Shiaw TSAI, Shao-Kuan LEE, Kuang-Wei YANG, Gary LIU, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
  • Patent number: 12431386
    Abstract: A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.
    Type: Grant
    Filed: July 5, 2024
    Date of Patent: September 30, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chin Lee, Ting-Ya Lo, Chi-Lin Teng, Cherng-Shiaw Tsai, Shao-Kuan Lee, Kuang-Wei Yang, Gary Liu, Hsin-Yen Huang, Hsiao-Kang Chang, Shau-Lin Shue
  • Publication number: 20250167042
    Abstract: A method for manufacturing a semiconductor device includes: forming a conductive structure; forming an interconnect layer on the conductive structure, the interconnect layer including a conductive interconnect that is electrically connected to the conductive structure; and forming multiple conductive features and multiple spacer features on the interconnect layer, adjacent two of the conductive features being spaced apart from each other by a corresponding one of the spacer features, one of the conductive features being electrically connected to the conductive interconnect, each of the spacer features including a dielectric spacer layer contacting lateral surfaces of two of the conductive features that are adjacent to the spacer feature, and a cover segment disposed on the dielectric spacer layer and cooperating with the dielectric spacer layer to define an air gap between the two of the conductive features that are adjacent to the spacer feature.
    Type: Application
    Filed: November 17, 2023
    Publication date: May 22, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Ya LO, Gary LIU, Chi-Lin TENG, Zi-Yi YANG, Chuan-Pu CHOU, Hsin-Yen HUANG, Chia-Tien WU, Hsiao-Kang CHANG, Shao-Kuan LEE, Chia-Chen LEE
  • Publication number: 20250149436
    Abstract: A method for manufacturing an interconnect structure includes: forming sacrificial portions and electrically conductive portions on a base structure such that the sacrificial portions are disposed to alternate with the electrically conductive portions in a first direction, and such that each of the sacrificial portions and the electrically conductive portions is elongated in a second direction transverse to the first direction; forming blocking portions respectively on the sacrificial portions; forming a sacrificial layer to cover the electrically conductive portions and the blocking portions; forming an electrically conductive via which extends through the sacrificial layer so as to permit the electrically conductive via to be electrically connected to one of the electrically conductive portions; after forming the electrically conductive via, performing a removal process to remove the sacrificial layer, the blocking portions and the sacrificial portions so as to form a cavity; and forming a dielectric portio
    Type: Application
    Filed: November 6, 2023
    Publication date: May 8, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Gary LIU, Ting-Ya LO, Shao-Kuan LEE, Zi-Yi YANG, Chi-Lin TENG, Kuang-Wei YANG, Hsin-Yen HUANG, Hsiao-Kang CHANG, Ming-Han LEE, Shau-Lin SHUE
  • Publication number: 20250132247
    Abstract: An interconnection structure is provided to include a substrate, a first metal trench, a boron nitride dielectric, a second metal trench, and a metal via. The substrate is formed with a first metal trench. The boron nitride dielectric is disposed over the substrate. The second metal trench is formed in the boron nitride dielectric. The metal via is disposed to interconnect the first metal trench and the second metal trench.
    Type: Application
    Filed: October 24, 2023
    Publication date: April 24, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Lin TENG, Gary LIU, Ting-Ya LO, Yen-Ju WU, Shao-Kuan LEE, Kuang-Wei YANG, Hsin-Yen HUANG, Hsiao-Kang CHANG
  • Publication number: 20250096140
    Abstract: An interconnect structure, along with methods of forming such, are described. The structure includes a dielectric layer, a conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer, wherein the conductive layer includes a first portion and a second portion adjacent the first portion. The structure also includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a dielectric material disposed between and in contact with the first and second barrier layers, wherein a bottom surface of the second barrier layer and a bottom surface of the dielectric material are substantially co-planar.
    Type: Application
    Filed: September 17, 2023
    Publication date: March 20, 2025
    Inventors: Hsien-Chang WU, Shih-Kang FU, Shin-Yi YANG, Gary LIU, Ting-Ya LO, Ming-Han LEE
  • Publication number: 20240363400
    Abstract: A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.
    Type: Application
    Filed: July 5, 2024
    Publication date: October 31, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Cherng-Shiaw TSAI, Shao-Kuan LEE, Kuang-Wei YANG, Gary LIU, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
  • Patent number: 12062572
    Abstract: A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: August 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chin Lee, Ting-Ya Lo, Chi-Lin Teng, Cherng-Shiaw Tsai, Shao-Kuan Lee, Kuang-Wei Yang, Gary Liu, Hsin-Yen Huang, Hsiao-Kang Chang, Shau-Lin Shue
  • Publication number: 20240234203
    Abstract: A method for manufacturing a semiconductor device includes: preparing a conductive structure that includes a plurality of conductive features, adjacent two of which are spaced apart from each other by a corresponding one of a plurality of recesses; conformally forming a dielectric capping layer on the conductive structure; forming a dielectric cover layer on the dielectric capping layer to fill the recesses; and removing a portion of the dielectric cover layer and a portion of the dielectric capping layer to expose the conductive features, so as to form a plurality of spacer features respectively filled in the recesses; wherein each of the dielectric capping layer and the dielectric cover layer is made of a dielectric material doped with metal oxide.
    Type: Application
    Filed: January 5, 2023
    Publication date: July 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Ya LO, Shao-Kuan LEE, GARY LIU, Zi-Yi YANG, Kuang-Wei YANG, Jing-Ting SU, Chi-Lin TENG, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
  • Publication number: 20230260831
    Abstract: A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.
    Type: Application
    Filed: February 17, 2022
    Publication date: August 17, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Cherng-Shiaw TSAI, Shao-Kuan LEE, Kuang-Wei YANG, Gary LIU, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
  • Publication number: 20230233813
    Abstract: An intravenous (IV) catheter assembly may include a catheter adapter and a catheter extending from the distal end of the catheter adapter. The intravenous (IV) catheter assembly may include an introducer needle. The elongated shaft may include a flashback notch, and the flashback notch may include a distal end and a proximal end. The flashback notch may include a smooth tapered edge extending from the distal end in a direction that increases a depth of the flashback notch. The smooth tapered edge may extend along at least half of an entire length of the flashback notch between the distal end and the proximal end.
    Type: Application
    Filed: December 5, 2022
    Publication date: July 27, 2023
    Inventors: Xiwei Chen, Linda Kunardi, Xue Guang John Ong, Bo Yan, Gary Liu
  • Publication number: 20170247735
    Abstract: Methods for recombinant and enzymatic production of mogroside compounds and compositions containing mogroside compounds are provided by this invention.
    Type: Application
    Filed: September 30, 2015
    Publication date: August 31, 2017
    Inventors: Jens Houghton-Larsen, Katarzyna Krzystanek, Angelika Semmler, Iver Klavs Riishede Hansen, Soren Damkiaer, Gary Liu, Yaoquan Liu, Jorgen Hansen, Sathish Kumar, Muthuswamy Panchapagesa Murali, Nina Nicoline Rasmussen
  • Patent number: 7946094
    Abstract: The invention provides a topside beam. The topside beam comprises: an upper topside beam that is comprised of an upper web beam (10), an upper left wing beam (12) and upper right wing beam (11), wherein the section of the upper web beam (10) has a shape of an inverted “L”; the upper left wing beam (12) and the upper right wing beam (11) are oppositely connected to the two sides adjacent to the lower end of the upper web beam (10) respectively; the upper left wing beam (12) opposite to the upper web beam (10) inclines downwardly; and the upper right wing beam (11) is located at 90° with the upper web beam. And a lower topside beam that is comprised of a lower web beam (20) and a lower right wing beam (21), wherein the lower right wing beam (21) is connected to the right side adjacent to the upper end of the lower web beam (20); and the lower right wing beam (21) opposite to the lower web beam (20) inclines upwardly and is parallel to the upper left wing beam (12).
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: May 24, 2011
    Assignees: China International Marine Containers (Group) Ltd., Qingdao CIMC Reefer Trailer Co., Ltd., Qingdao CIMC Reefer Container Manufacture Co., Ltd., Qingdao CIMC Special Reefer Co., Ltd.
    Inventors: Tianhua Huang, Robert Wang, Ryan Xu, Jack Zhang, Gary Liu
  • Publication number: 20100205902
    Abstract: The invention provides a topside beam. The topside beam comprises: an upper topside beam that is comprised of an upper web beam (10), an upper left wing beam (12) and upper right wing beam (11), wherein the section of the upper web beam (10) has a shape of an inverted “L”; the upper left wing beam (12) and the upper right wing beam (11) are oppositely connected to the two sides adjacent to the lower end of the upper web beam (10) respectively; the upper left wing beam (12) opposite to the upper web beam (10) inclines downwardly; and the upper right wing beam (11) is located at 90° with the upper web beam. And a lower topside beam that is comprised of a lower web beam (20) and a lower right wing beam (21), wherein the lower right wing beam (21) is connected to the right side adjacent to the upper end of the lower web beam (20); and the lower right wing beam (21) opposite to the lower web beam (20) inclines upwardly and is parallel to the upper left wing beam (12).
    Type: Application
    Filed: January 7, 2010
    Publication date: August 19, 2010
    Applicants: CHINA INTERNATIONAL MARINE CONTAINERS (GROUP) LTD., QINGDAO CIMC REEFER TRAILER CO., LTD., QINGDAO CIMC REEFER CONTAINER MANUFACTURE CO., LTD, QINGDAO CIMC SPECIAL REEFER CO., LTD.
    Inventors: T.H. Huang, Robert Wang, Ryan Xu, Jack Zhang, Gary Liu
  • Patent number: D1032510
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: June 25, 2024
    Assignee: SHENZHEN CHIEF POWER ELECTRONICS CO., LTD
    Inventor: Gary Liu
  • Patent number: D1042335
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: September 17, 2024
    Assignee: SHENZHEN CHIEF POWER ELECTRONICS CO., LTD
    Inventor: Gary Liu
  • Patent number: D1069696
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: April 8, 2025
    Assignee: Shenzhen Chief-power Electronics Co., Ltd
    Inventor: Gary Liu
  • Patent number: D1069697
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: April 8, 2025
    Assignee: Shenzhen Chief-power Electronics Co., Ltd
    Inventor: Gary Liu
  • Patent number: D1073594
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: May 6, 2025
    Assignee: Shenzhen Chief-power Electronics Co., Ltd
    Inventor: Gary Liu