Abstract: The present invention relates to a method and apparatus for a system utilizing a microprocessor having a faster maximum operating frequency and a numeric data processor having a slower maximum operating frequency which runs the system at the lower clocking frequency only during those times when both the microprocessor and the numeric data processor are required to perform processing functions and runs the system at the higher clocking frequency when only the microprocessor is required. Therefore the method and apparatus of the invention provides greater operating efficiency for the microprocessor, while not sacrificing the interface capabilities of the numeric data processor. In the apparatus of the present invention, the clocking frequencies are generated by a clocking generator which is coupled to both the microprocessor and the numeric data processor. The generator responds to signals from a control source to provide either the faster or the slower clocking frequency.

Abstract: A detector for detecting a valid synchronizing pattern in a data frame in which a synchronizing bit pattern is multiplexed including a first register to receive the data and the synchronization bits, a pattern detector connected to the first register for detecting the synchronizing bit pattern in the first register, a second register, a source of clock pulses coupled to both said first and second registers, the elements of the second register being set to a first binary state and a density detector coupled to the second register.