Patents by Inventor Gary M. Dolny
Gary M. Dolny has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11646371Abstract: A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.Type: GrantFiled: April 26, 2022Date of Patent: May 9, 2023Assignees: Amplexia, LLC, X-FAB Global Services GmbHInventors: Brendan Toner, Zhengchao Liu, Gary M Dolny, William R Richards, Jr.
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Publication number: 20230054381Abstract: Devices and methods for providing a power transistor structure with a shallow source region include implanting a dopant of a first dopant polarity into a drift region on a source side of a gate structure to form a body region, the body region being self-aligned to, and extending under, the gate structure, and producing a shallow body region wherein the source side hybrid contact mitigates punch through of the shallow self-aligned body region and suppresses triggering of a parasitic bipolar. A retrograde body well, of the first dopant polarity, may be disposed beneath, and noncontiguous with, the shallow self-aligned body region, wherein the retrograde body well improves the electric field profile of the shallow self-aligned body region. A variety of power transistor structures are produced from such devices and methods.Type: ApplicationFiled: November 2, 2022Publication date: February 23, 2023Applicants: Amplexia, LLC, X-FAB Global Services GmbHInventors: Brendan TONER, Zhengchao LIU, Gary M DOLNY, William R RICHARDS, Manoj Chandrika Reghunathan, Stefan Eisenbrandt, Christoph Ellmers
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Patent number: 11522053Abstract: Devices and methods for providing a power transistor structure with a shallow source region include implanting a dopant of a first dopant polarity into a drift region on a source side of a gate structure to form a body region, the body region being self-aligned to, and extending under, the gate structure, and producing a shallow body region wherein the source side hybrid contact mitigates punch through of the shallow self-aligned body region and suppresses triggering of a parasitic bipolar. A retrograde body well, of the first dopant polarity, may be disposed beneath, and noncontiguous with, the shallow self-aligned body region, wherein the retrograde body well improves the electric field profile of the shallow self-aligned body region. A variety of power transistor structures are produced from such devices and methods.Type: GrantFiled: December 3, 2021Date of Patent: December 6, 2022Assignees: Amplexia, LLC, X-FAB Global Services GmbHInventors: Brendan Toner, Zhengchao Liu, Gary M. Dolny, William R. Richards, Manoj Chandrika Reghunathan, Stefan Eisenbrandt, Christoph Ellmers
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Publication number: 20220254914Abstract: A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.Type: ApplicationFiled: April 26, 2022Publication date: August 11, 2022Applicants: Amplexia, LLC, X-FAB Global Services GmbHInventors: Brendan TONER, Zhengchao LIU, Gary M DOLNY, William R RICHARDS, JR.
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Publication number: 20220181444Abstract: Devices and methods for providing a power transistor structure with a shallow source region include implanting a dopant of a first dopant polarity into a drift region on a source side of a gate structure to form a body region, the body region being self-aligned to, and extending under, the gate structure, and producing a shallow body region wherein the source side hybrid contact mitigates punch through of the shallow self-aligned body region and suppresses triggering of a parasitic bipolar. A retrograde body well, of the first dopant polarity, may be disposed beneath, and noncontiguous with, the shallow self-aligned body region, wherein the retrograde body well improves the electric field profile of the shallow self-aligned body region. A variety of power transistor structures are produced from such devices and methods.Type: ApplicationFiled: December 3, 2021Publication date: June 9, 2022Applicants: Silicet, LLC, X-FAB Global Services GmbHInventors: Brendan TONER, Zhengchao LIU, Gary M. DOLNY, William R. RICHARDS, Manoj Chandrika Reghunathan, Stefan Eisenbrandt, Christoph Ellmers
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Patent number: 11322611Abstract: A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.Type: GrantFiled: November 12, 2020Date of Patent: May 3, 2022Assignees: Silicet, LLC, X-FAB Global Services GmbHInventors: Brendan Toner, Zhengchao Liu, Gary M Dolny, William R Richards, Jr.
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Publication number: 20210134999Abstract: A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.Type: ApplicationFiled: November 12, 2020Publication date: May 6, 2021Applicants: Silicet, LLC, X-FAB Global Services GmbHInventors: Brendan TONER, Zhengchao LIU, Gary M DOLNY, William R RICHARDS, JR.
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Patent number: 10892362Abstract: A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.Type: GrantFiled: April 10, 2020Date of Patent: January 12, 2021Assignees: Silicet, LLC, X-FAB Global Services GmbHInventors: Brendan Toner, Zhengchao Liu, Gary M Dolny, William R Richards, Jr.
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Patent number: 10510869Abstract: Devices, structures, and methods thereof for providing a Schottky or Schottky-like contact as a source region and/or a drain region of a power transistor are disclosed. A power transistor structure comprises a substrate of a first dopant polarity, a drift region formed on or within the substrate, a body region formed on or within the drift region, a gate structure formed on or within the substrate, a source region adjacent to the gate structure, a drain region formed adjacent to the gate structure. At least one of the source region and the drain region is formed from a Schottky or Schottky-like contact substantially near a surface of the substrate, comprising a silicide layer and an interfacial dopant segregation layer. The Schottky or Schottky-like contact is formed by low-temperature annealing a dopant segregation implant in the source and/or drain region.Type: GrantFiled: March 21, 2018Date of Patent: December 17, 2019Assignee: SILICET, LLCInventors: Gary M. Dolny, William R. Richards, Jr., Randall Milanowski
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Publication number: 20180212041Abstract: Devices, structures, and methods thereof for providing a Schottky or Schottky-like contact as a source region and/or a drain region of a power transistor are disclosed. A power transistor structure comprises a substrate of a first dopant polarity, a drift region formed on or within the substrate, a body region formed on or within the drift region, a gate structure formed on or within the substrate, a source region adjacent to the gate structure, a drain region formed adjacent to the gate structure. At least one of the source region and the drain region is formed from a Schottky or Schottky-like contact substantially near a surface of the substrate, comprising a silicide layer and an interfacial dopant segregation layer. The Schottky or Schottky-like contact is formed by low-temperature annealing a dopant segregation implant in the source and/or drain region.Type: ApplicationFiled: March 21, 2018Publication date: July 26, 2018Applicant: Silicet, LLCInventors: Gary M. DOLNY, William R. RICHARDS, JR., Randall MILANOWSKI
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Patent number: 9947787Abstract: Devices, structures, and methods thereof for providing a Schottky or Schottky-like contact as a source region and/or a drain region of a power transistor are disclosed. A power transistor structure comprises a substrate of a first dopant polarity, a drift region formed on or within the substrate, a body region formed on or within the drift region, a gate structure formed on or within the substrate, a source region adjacent to the gate structure, a drain region formed adjacent to the gate structure. At least one of the source region and the drain region is formed from a Schottky or Schottky-like contact substantially near a surface of the substrate, comprising a silicide layer and an interfacial dopant segregation layer. The Schottky or Schottky-like contact is formed by low-temperature annealing a dopant segregation implant in the source and/or drain region.Type: GrantFiled: April 28, 2017Date of Patent: April 17, 2018Assignee: SILICET, LLCInventors: Gary M. Dolny, William R. Richards, Jr., Randall Milanowski
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Publication number: 20170323970Abstract: Devices, structures, and methods thereof for providing a Schottky or Schottky-like contact as a source region and/or a drain region of a power transistor are disclosed. A power transistor structure comprises a substrate of a first dopant polarity, a drift region formed on or within the substrate, a body region formed on or within the drift region, a gate structure formed on or within the substrate, a source region adjacent to the gate structure, a drain region formed adjacent to the gate structure. At least one of the source region and the drain region is formed from a Schottky or Schottky-like contact substantially near a surface of the substrate, comprising a silicide layer and an interfacial dopant segregation layer. The Schottky or Schottky-like contact is formed by low-temperature annealing a dopant segregation implant in the source and/or drain region.Type: ApplicationFiled: April 28, 2017Publication date: November 9, 2017Applicant: Silicet, LLCInventors: Gary M. DOLNY, William R. RICHARDS, JR., Randall MILANOWSKI
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Patent number: 8884365Abstract: A field effect transistor (FET) includes a body region of a first conductivity type disposed within a semiconductor region of a second conductivity type and a gate trench extending through the body region and terminating within the semiconductor region. The FET also includes a flared shield dielectric layer disposed in a lower portion of the gate trench, the flared shield dielectric layer including a flared portion that extends under the body region. The FET further includes a conductive shield electrode disposed in the trench and disposed, at least partially, within the flared shield dielectric.Type: GrantFiled: May 10, 2013Date of Patent: November 11, 2014Assignee: Fairchild Semiconductor CorporationInventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
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Patent number: 8803207Abstract: In one general aspect, an apparatus can include a trench disposed in a semiconductor region, a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench, and a gate dielectric lining a upper portion of the sidewall of the trench. The apparatus can also include a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer, and an inter-electrode dielectric (IED) disposed in the trench over the shield electrode where the shield electrode has a curved top surface.Type: GrantFiled: April 6, 2011Date of Patent: August 12, 2014Assignee: Fairchild Semiconductor CorporationInventors: Thomas E. Grebs, Nathan Lawrence Kraft, Rodney Ridley, Gary M. Dolny, Joseph A. Yedinak, Christopher Boguslaw Kocon, Ashok Challa
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Publication number: 20130248991Abstract: A field effect transistor (FET) includes a body region of a first conductivity type disposed within a semiconductor region of a second conductivity type and a gate trench extending through the body region and terminating within the semiconductor region. The FET also includes a flared shield dielectric layer disposed in a lower portion of the gate trench, the flared shield dielectric layer including a flared portion that extends under the body region. The FET further includes a conductive shield electrode disposed in the trench and disposed, at least partially, within the flared shield dielectric.Type: ApplicationFiled: May 10, 2013Publication date: September 26, 2013Applicant: Fairchild Semiconductor CorporationInventors: Hamza YILMAZ, Daniel CALAFUT, Christopher Boguslaw KOCON, Steven P. SAPP, Dean E. PROBST, Nathan L. KRAFT, Thomas E. GREBS, Rodney S. RIDLEY, Gary M. DOLNY, Bruce D. MARCHANT, Joseph A. YEDINAK
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Patent number: 8441069Abstract: A field effect transistor includes a gate trench extending into a semiconductor region. The gate trench has a recessed gate electrode disposed therein. A source region in the semiconductor region flanks each side of the gate trench. A conductive material fills an upper portion of the gate trench so as to make electrical contact with the source regions along upper sidewalls of the gate trench. The conductive material is insulated from the recessed gate electrode.Type: GrantFiled: October 21, 2011Date of Patent: May 14, 2013Assignee: Fairchild Semiconductor CorporationInventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
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Publication number: 20120220091Abstract: A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench.Type: ApplicationFiled: March 12, 2012Publication date: August 30, 2012Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridley, Steven P. Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter H. Wilson, Joseph A. Yedinak, J.Y. Jung, H.C. Jang, Babak S. Sani, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
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Publication number: 20120153384Abstract: A semiconductor package device houses a die which comprises a power device, and the die further includes a silicon region over a substrate, a first plurality of trenches extending in the silicon region; a contiguous sinker trench extending along the perimeter of the die so as to completely surround the first plurality of trenches, the sinker trench extending from a top surface of the die through the silicon region, the sinker trench being lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench; and a plurality of interconnect balls arranged in a grid array, an outer group of the plurality of interconnect balls electrically connecting to the conductive material in the sinker trench.Type: ApplicationFiled: January 10, 2012Publication date: June 21, 2012Inventors: Thomas E. Grebs, Gary M. Dolny
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Publication number: 20120104490Abstract: A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.Type: ApplicationFiled: October 21, 2011Publication date: May 3, 2012Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
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Patent number: 8148233Abstract: A semiconductor power device includes a plurality of groups of stripe-shaped gate trenches extending in a silicon region over a substrate, and a plurality of stripe-shaped sinker trenches each extending between two adjacent groups of the plurality of groups of stripe-shaped gate trenches. The plurality of stripe-shaped sinker trenches extend from a top surface of the silicon region through the silicon region and terminate within the substrate. The plurality of stripe-shaped sinker trenches are lined with an insulator along the sinker trench sidewalls so that a conductive material filling each sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench.Type: GrantFiled: July 7, 2011Date of Patent: April 3, 2012Assignee: Fairchild Semiconductor CorporationInventors: Thomas E. Grebs, Gary M. Dolny