Patents by Inventor Gary M. Papenfuss

Gary M. Papenfuss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9590924
    Abstract: Methods and systems for a network device are provided. The network device includes a stage one arbiter for a base-port having a plurality of sub-ports for determining if there are any pending requests; blocking any other requests from a same receive queue destined for a same sub-port, same transmit queue when there are any pending requests; selecting a group of requests with a highest priority and available resources; selecting highest priority requests; selecting an oldest one of the highest priority requests; sending the selected requests to a stage two arbiter for selecting a request with a highest priority and when there are requests that have a same priority, selecting an oldest request for processing.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: March 7, 2017
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Gary M. Papenfuss, Leo J. Slechta, Jr.
  • Patent number: 9172655
    Abstract: System and methods for providing quality of service (QOS) in networks. The method includes determining whether a transmit segment of a port of a network device has received a grant from a scheduler to transmit a packet. The port includes a plurality of sub-ports that share the transmit segment to transmit packets and a receive segment to receive packets. When the transmit buffer has received the grant, a virtual queue associated with the grant is mapped to a QOS bin that includes a minimum bandwidth limit threshold value, a maximum bandwidth threshold value, and a counter for counting actual bandwidth consumed. The QOS bin monitors bandwidth consumed by a source traffic group for adjusting QOS priority and the source traffic group includes the virtual queue.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: October 27, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Gary M. Papenfuss
  • Patent number: 9118586
    Abstract: A method and system for routing frames based on a port's speed using a switch element. The method includes receiving a portion of a frame in a receive buffer of a port; determining a frame length threshold value; and setting up a status bit based on the port's speed, the frame length threshold value and an amount of the frame received. The status bit is sent to a transmit segment of the switch element and the frame length threshold value is proportional to the port's speed. Also, if the receive buffer is almost full when the frame arrives at the receive port, then a cut status is based on the frame's end of frame (“EOF”) value.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: August 25, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Craig M. Verba, Gary M. Papenfuss
  • Patent number: 9094294
    Abstract: Method and system for reporting out-of-credit condition for a network device connected to a network. An indication to an out-of credit logic is provided that a first sub-port operating using a first protocol is out of credit to transmit information from a transmit segment. The first sub-port is a part of a base-port that includes a plurality of sub-ports that can be configured to operate at more than one operating speed to process packets complying with different protocols. The out-of-credit logic determines when the first sub-port is out-of-credit for a threshold period of time, and reports that the sub-port is out-of-credit to a processor of the network device.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: July 28, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Bret E. Indrelee, Leo J. Slechta, Jr., Gary M. Papenfuss, Edward C. Ross
  • Patent number: 8995425
    Abstract: Methods and systems for a network device are provided. The network device includes a stage one arbiter for a base-port for determining if there are any pending requests; blocking any other requests from a same receive queue destined for a same sub-port, same physical transmit queue, and same virtual transmit queue when there are any pending requests; selecting a group of requests with a highest priority and available resources; selecting at least two of the highest priority requests; selecting an oldest one of the requests having the same priority when there are requests with a same priority; sending the selected requests to a stage two arbiter for the base-port; and determining if any new requests have been made or if any previously pending requests have been removed.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: March 31, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Gary M. Papenfuss, Leo J. Slechta, Jr.
  • Patent number: 8995457
    Abstract: Methods and systems for a network device are provided. The network device includes a plurality of base-ports, where each base-port is coupled to a plurality of network links and each base-port has a plurality of sub-ports. The network device includes a transmit segment having a modifier shared by the plurality of sub-ports for modifying frames that are modified prior to being transmitted using the plurality of network links. The modifier uses a translation data structure to obtain information to modify a frame before transmission, where the translation data structure includes a plurality of entries, each entry stored in a queue that is uniquely identified by an identifier, and the identifier is extracted from a grant to transmit the frame and then used to obtain frame modification information from one of the plurality of entries. Frame modification when performed by the modifier depends on a frame type and sub-port configuration.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: March 31, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Gary M. Papenfuss, William J. Andersen
  • Patent number: 8989191
    Abstract: Method and system for a network device configured to control access to other devices in a network is provided. The network device includes a port configured to receive a frame. The port includes a plurality of sub-ports configured to operate as independent ports for sending and receiving frames using one of a plurality of network links at a plurality of rates and complying with a plurality of protocols. The network device also includes a source address look up table (ALUT) and a destination address look up table (LLUT), wherein when the frame is received the network device is configured to compare a source identifier of the frame and a destination identifier of the frame to the ALUT and the LLUT. When one ALUT table entry matches the source identifier of the frame, the network device outputs a bit map of zones based on the source identifier of the frame, compares the output bit map of zones with a zone bit map of the LLUT, and when there are any matching bits between the two maps, transmits the frame.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: March 24, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Gary M. Papenfuss
  • Patent number: 8976800
    Abstract: A switching element and methods thereof are provided. The switching element includes a port from among a plurality of ports, which when configured to operate as a network protocol port sends and receives network information and when configured to operate as a storage protocol port sends and receives storage information. The port includes a control segment for generating a control signal for setting an operating mode of a serial and de-serializer (SERDES). The operating mode of the SERDES is selected based on whether the port is configured to operate as a network protocol port or as a storage protocol port.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: March 10, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Gary M. Papenfuss
  • Patent number: 8644317
    Abstract: A fiber channel switch element and method for routing fiber channel frames is provided. The switch element includes a receive segment that can add a virtual storage area network (“VSAN”) tagging header to frames that are received by the receive segment; and strip the VSAN tagging header before frames are sent to ports that do not support virtual fabric capability. The receive segment includes a table used for matching fabric extension parameters. An incoming frame's VSAN identity value is compared to a control word entry to generate a value used for routing the incoming frame. The table is used to determine if a frame is part of a virtual fabric. The routing table for each port is used to route frames and the routing table includes entries for supported virtual fabrics.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: February 4, 2014
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Craig M. Verba, Gary M. Papenfuss, Ernest G. Kohlwey, Edward C. Ross
  • Patent number: 8391300
    Abstract: A switching element and methods thereof are provided. The switching element includes a port from among a plurality of ports, which when configured to operate as a network protocol port sends and receives network information and when configured to operate as a storage protocol port sends and receives storage information. The port includes a control segment for generating a control signal for setting an operating mode of a serial and de-serializer (SERDES). The operating mode of the SERDES is selected based on whether the port is configured to operate as a network protocol port or as a storage protocol port.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: March 5, 2013
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Gary M. Papenfuss
  • Patent number: 8116206
    Abstract: A method for routing frames is provided. The method comprises: receiving a frame at a receive port segment of a port for a switch element; generating a tag based on information included in the frame, where the tag identifies a location where the frame is stored in the receive port segment; transmitting the tag to a destination port for the frame; generating a request for the frame, wherein the destination port generates the request for the frame; transmitting the request for the frame to the port that received the frame, where a field in the request differentiates the request for the frame from the tag generated by the receive port segment of the port that received the frame; and transmitting the frame stored at the receive port segment, in response to the request sent by the destination port.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: February 14, 2012
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Gary M. Papenfuss
  • Patent number: 8005105
    Abstract: A fiber channel switch element for routing fiber channel frame is provided. The switch element includes a fiber channel port that can be configured to support plural data transfer rates. The data transfer rate may be 1 G, 2 G, 4 G, 8 G or 10 G. The switch element includes a clock configuration module for providing a clock signal that is based on the data transfer rate. A receive segment of the fiber channel port sends a signal to a transmit segment to avoid an under flow condition. The receive segment also waits for a certain frame length after a fiber channel frame is written and before the fiber channel frame is read, depending upon a data transfer rate of a source port. Multiple lanes may be configured as a single 10 G multi lane port or as multiple individual ports.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: August 23, 2011
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Gary M. Papenfuss, Ernest G. Kohlwey
  • Patent number: 7990975
    Abstract: A fibre channel switch element and method for routing fibre channel frames is provided. The switch element includes a receive segment that can add a virtual storage area network (“VSAN”) tagging header to frames that are received by the receive segment; and strip the VSAN tagging header before frames are sent to ports that do not support virtual fabric capability. The receive segment includes a table used for matching fabric extension parameters. An incoming frame's VSAN identity value is compared to a control word entry to generate a value used for routing the incoming frame. The table is used to determine if a frame is part of a virtual fabric. The routing table for each port is used to route frames and the routing table includes entries for supported virtual fabrics.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: August 2, 2011
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Craig M. Verba, Gary M. Papenfuss, Ernest G. Kohlwey, Edward C. Ross
  • Patent number: 7936771
    Abstract: A method and system for transmitting frames using a fiber channel switch element is provided. The switch element includes a port having a receive segment and a transmit segment, wherein the fiber channel switch element determines if a port link has been reset; determines if a flush state has been enabled for the port; and removes frames from a buffer, if the flush state has been enabled for the port. For a flush state operation, frames are removed from a receive buffer of the fiber channel port as if it is a typical fiber channel frame transfer. The removed frames are sent to a processor for analysis. The method also includes, setting a control bit for activating frame removal from the transmit buffer; and diverting frames that are waiting in the transmit buffer and have not been able to move from the transmit buffer.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: May 3, 2011
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Gary M. Papenfuss
  • Patent number: 7894348
    Abstract: A method and system for routing fiber channel frames using a fiber channel switch element is provided. The switch element includes logic for comparing a credit counter value with a first threshold value to enable a credit limiting feature; and a first counter that receives a signal after a frame has departed from a transmit segment and maintains a maximum value for a certain duration that is based on the first threshold value. The method includes enabling a credit limiting feature, wherein frame transmission from a certain source is delayed when the credit limiting feature is enabled. The first counter is incremented every time a frame departs and holds its maximum value based on the threshold value. When the first counter is at the maximum value, a credit-limiting signal is used to enable the credit limiting feature by setting a control bit in a control register.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: February 22, 2011
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Gary M. Papenfuss
  • Patent number: 7822057
    Abstract: A method and system for keeping an arbitrated loop open during a frame gap using a fiber channel switch element is provided. The switch element includes a port control module having a receive and transmit segment, wherein the transmit segment activates a timer whose value determines a duration during which the arbitrated loop remains open; determines if a last frame from a sequence of frames from a source port has been transmitted; modifies the timer value if a higher priority frame for transmission is unavailable; and keeps the arbitrated loop open until the timer reaches a certain value. If a higher priority frame is available for transmission before the timer value is modified then the higher priority frame is transmitted and the timer value is re-initialized.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: October 26, 2010
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Ernest G. Kohlwey, Gary M. Papenfuss
  • Patent number: 7684401
    Abstract: A fiber channel switch element and method for routing fiber channel frames is provided. The switch element includes a receive segment that can add a virtual storage area network (“VSAN”) tagging header to frames that are received by the receive segment; and strip the VSAN tagging header before frames are sent to ports that do not support virtual fabric capability. The receive segment includes a table used for matching fabric extension parameters. An incoming frame's VSAN identity value is compared to a control word entry to generate a value used for routing the incoming frame. The table is used to determine if a frame is part of a virtual fabric. The routing table for each port is used to route frames and the routing table includes entries for supported virtual fabrics.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: March 23, 2010
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Craig M. Verba, Gary M. Papenfuss, Ernest G. Kohlwey, Edward C. Ross
  • Publication number: 20100040074
    Abstract: A method and system for routing frames based on a port's speed using a fibre channel switch element is provided. The method includes, receiving a portion of a frame in a receive buffer of a port; determining a frame length threshold; and setting up a status bit based on the port's speed, the frame length threshold and an amount of frame received. The status bit is sent to a transmit segment of the fibre channel switch element and the frame length threshold value is inversely proportional to the port's speed. Also, if the receive buffer is almost full when a frame arrives at the receive port, then a cut status is based on a frames end of frame (“EOF”) value.
    Type: Application
    Filed: July 14, 2009
    Publication date: February 18, 2010
    Inventors: Frank R. Dropps, Craig M. Verba, Gary M. Papenfuss
  • Patent number: 7649903
    Abstract: Method and system for routing fiber channel frames using a fiber channel switch element is provided. The method includes, inserting a time stamp value in a fiber channel frame that is received at a receive segment of the fibre channel switch element; determining if a timeout occurs after a frame arrives at a receive buffer; and processing the frame if the timeout occurred. The method also includes, determining if a delta time value, which provides an accumulated wait time for a frame, is present in frame data; subtracting the delta time stamp value from a global time stamp value and using the resulting time stamp value to determine frame timeout status in the fiber channel switch element. A timeout checker circuit declares a timeout after comparing a time stamp value that is inserted in a fiber channel frame with a programmed time out value and a global counter value.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: January 19, 2010
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Craig M. Verba, Gary M. Papenfuss, Ernest G Kohlwey, Mark A. Owen
  • Publication number: 20090290584
    Abstract: A fibre channel switch element for routing fibre channel frame is provided. The switch element includes a fibre channel port that can be configured to support plural data transfer rates. The data transfer rate may be 1 G, 2 G, 4 G, 8 G or 10 G. The switch element includes a clock configuration module for providing a clock signal that is based on the data transfer rate. A receive segment of the fibre channel port sends a signal to a transmit segment to avoid an under flow condition. The receive segment also waits for a certain frame length after a fibre channel frame is written and before the fibre channel frame is read, depending upon a data transfer rate of a source port. Multiple lanes may be configured as a single 10G multi lane port or as multiple individual ports.
    Type: Application
    Filed: May 27, 2009
    Publication date: November 26, 2009
    Inventors: Frank R. Dropps, Gary M. Papenfuss, Ernest G. Kohlwey