Abstract: The present invention teaches a method and structure of enhancing the current gain characteristics of a bipolar junction transistor using a semiconductor substrate comprising a base, an emitter and a collector and an interface at the emitter, such that a carrier current conducts between the base and the emitter. Further, a first polysilicon layer is formed superjacent the interface, and is implanted with O.sub.2. Subsequently, the substrate is heated such that the emitter interface is obstructed by a silicon dioxide formation, thereby blocking a portion of carrier current from passing through the interface.

Abstract: The present invention teaches a method and structure of enhancing the current gain characteristics of a bipolar junction transistor. The method comprises the step of forming a patterned silicon dioxide layer superjacent a semiconductor substrate comprising a base, an emitter and a collector, such that a carrier current conducts between the base and the emitter. The silicon dioxide layer forms an interface on the substrate at the emitter. Further, a first polysilicon layer is formed superjacent both the patterned silicon dioxide layer and the interface, and is implanted with O.sub.2. Subsequently, the substrate is heated such that the emitter interface is obstructed by a silicon dioxide formation, thereby blocking a portion of carrier current from passing through the interface.

Abstract: An integrated circuit has a silicon mesa disposed on a substrate and a field insulator structure in proximity to the mesa and having an opening over a top mesa surface. The opening, which exposes sidewalls in the structure, is positioned with respect to the mesa and has dimensions such that the structure is disposed to overlap a region of the mesa along an outer mesa periphery. A layer of polysilicon extends along a top surface of the structure and into the opening and adjacent to the mesa top surface. An insulator is disposed between the poly layer and the mesa top surface, the insulator having a layer of thermal gate oxide disposed adjacent to the poly layer and having a layer of pyrogenic oxide disposed between the thermal gate oxide layer and the mesa top surface.

Abstract: A method of treating the sidewalls of a transistor site aperture to form a gate insulator and increase the resistivity of the aperture sidewalls simultaneously combines an initial thin layer of thermal oxide with a thicker layer of pyrogenic oxide and a final layer of thermal oxide.