Patents by Inventor Gary Maki
Gary Maki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11626403Abstract: A SEU tolerant structure has two logic sections that generate two output signals that are complementary such that a fault which affects one section cannot affect the other section. Adjacent NMOS regions or adjacent PMOS regions contain no logic inversions in the combinational logic or if logic inversions in the combinational logic are present where all gates following the inversion are SEU hard by design. The circuits can be realized using one of a Complex CMOS gate, pass transistor logic, Multiplexor logic, AND-OR logic or OR-AND logic.Type: GrantFiled: May 19, 2021Date of Patent: April 11, 2023Assignee: ICs LLCInventors: Sterling Whitaker, Gary Maki
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Patent number: 11552079Abstract: A SEU tolerant structure has two logic sections that generate two output signals that are complementary such that a fault which affects one section cannot affect the other section. Adjacent NMOS regions or adjacent PMOS regions contain no logic inversions in the combinational logic or if logic inversions in the combinational logic are present where all gates following the inversion are SEU hard by design. The circuits can be realized using one of a Complex CMOS gate, pass transistor logic, Multiplexor logic, AND-OR logic or OR-AND logic.Type: GrantFiled: May 14, 2021Date of Patent: January 10, 2023Assignee: ICs LLCInventors: Sterling Whitaker, Gary Maki
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Publication number: 20210272953Abstract: A SEU tolerant structure has two logic sections that generate two output signals that are complementary such that a fault which affects one section cannot affect the other section. Adjacent NMOS regions or adjacent PMOS regions contain no logic inversions in the combinational logic or if logic inversions in the combinational logic are present where all gates following the inversion are SEU hard by design. The circuits can be realized using one of a Complex CMOS gate, pass transistor logic, Multiplexor logic, AND-OR logic or OR-AND logic.Type: ApplicationFiled: May 14, 2021Publication date: September 2, 2021Applicant: ICs LLCInventors: Sterling Whitaker, Gary Maki
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Publication number: 20210272954Abstract: A SEU tolerant structure has two logic sections that generate two output signals that are complementary such that a fault which affects one section cannot affect the other section. Adjacent NMOS regions or adjacent PMOS regions contain no logic inversions in the combinational logic or if logic inversions in the combinational logic are present where all gates following the inversion are SEU hard by design. The circuits can be realized using one of a Complex CMOS gate, pass transistor logic, Multiplexor logic, AND-OR logic or OR-AND logic.Type: ApplicationFiled: May 19, 2021Publication date: September 2, 2021Inventors: Sterling Whitaker, Gary Maki
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Patent number: 11069683Abstract: A SEU tolerant structure has two logic sections that generate two output signals that are complementary such that a fault which affects one section cannot affect the other section. Adjacent NMOS regions or adjacent PMOS regions contain no logic inversions in the combinational logic or if logic inversions in the combinational logic are present where all gates following the inversion are SEU hard by design. The circuits can be realized using one of a Complex CMOS gate, pass transistor logic, Multiplexor logic, AND-OR logic or OR-AND logic.Type: GrantFiled: September 26, 2019Date of Patent: July 20, 2021Assignee: ICs LLCInventors: Sterling Whitaker, Gary Maki
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Publication number: 20200111786Abstract: A SEU tolerant structure has two logic sections that generate two output signals that are complementary such that a fault which affects one section cannot affect the other section. Adjacent NMOS regions or adjacent PMOS regions contain no logic inversions in the combinational logic or if logic inversions in the combinational logic are present where all gates following the inversion are SEU hard by design. The circuits can be realized using one of a Complex CMOS gate, pass transistor logic, Multiplexor logic, AND-OR logic or OR-AND logic.Type: ApplicationFiled: September 26, 2019Publication date: April 9, 2020Inventors: Sterling Whitaker, Gary Maki
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Publication number: 20070109865Abstract: A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine.Type: ApplicationFiled: September 25, 2006Publication date: May 17, 2007Inventors: Gary Maki, Jody Gambles, Sterling Whitaker
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Patent number: 6573773Abstract: A Single Event Upset (SEU) resistant latch circuit that uses the Single Event Resistant Topology (SERT) comprises a first circuit module electrically coupled to a second circuit module. In the SERT-1 embodiment, the first circuit module has two output terminals, including four cross-coupled p-channel (PMOS) transistors coupled with two n-channel (NMOS) transistors. The second circuit module has two output terminals, including four cross-coupled p-channel (PMOS) transistors coupled with two n-channel (NMOS) transistors. These four output terminals satisfy a set of state equations that can be used to obtain the SERT-1 State Table. In the SERT-2 embodiment, the first circuit module has two output terminals, including four cross-coupled n-channel (NMOS) transistors coupled with two p-channel (PMOS) transistors. The second circuit module has two output terminals, including four cross-coupled n-channel (NMOS) transistors coupled with two p-channel (PMOS) transistors.Type: GrantFiled: February 2, 2001Date of Patent: June 3, 2003Assignee: University of New MexicoInventors: Gary Maki, Kenneth Haas, Shi Quan, James Murguia
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Publication number: 20010033189Abstract: A Single Event Upset (SEU) resistant latch circuit that uses the Single Event Resistant Topology (SERT) comprises a first circuit module electrically coupled to a second circuit module. In the SERT-1 embodiment, the first circuit module has two output terminals, including four cross-coupled p-channel (PMOS) transistors coupled with two n-channel (NMOS) transistors. The second circuit module has two output terminals, including four cross-coupled p-channel (PMOS) transistors coupled with two n-channel (NMOS) transistors. These four output terminals satisfy a set of state equations that can be used to obtain the SERT-1 State Table. In the SERT-2 embodiment, the first circuit module has two output terminals, including four cross-coupled n-channel (NMOS) transistors coupled with two p-channel (PMOS) transistors. The second circuit module has two output terminals, including four cross-coupled n-channel (NMOS) transistors coupled with two p-channel (PMOS) transistors.Type: ApplicationFiled: February 2, 2001Publication date: October 25, 2001Inventors: Gary Maki, Kenneth Hass, Shi Quan, James Murguia