Patents by Inventor Gary Mark Dolry

Gary Mark Dolry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7166866
    Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: January 23, 2007
    Assignee: Intersil America
    Inventors: Jun Zeng, Gary Mark Dolry, Praveen MurAleedharan
  • Publication number: 20040238903
    Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.
    Type: Application
    Filed: July 2, 2004
    Publication date: December 2, 2004
    Applicant: Intersil Corporation
    Inventors: Jun Zeng, Gary Mark Dolry, Praveen MurAleedharan
  • Patent number: 6759719
    Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: July 6, 2004
    Assignee: Intersil Corporation
    Inventors: Jun Zeng, Gary Mark Dolry, Praveen MurAleedharan
  • Publication number: 20030127693
    Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.
    Type: Application
    Filed: December 20, 2002
    Publication date: July 10, 2003
    Applicant: INTERSIL CORPORATION
    Inventors: Jun Zeng, Gary Mark Dolry, Praveen MurAleedharan
  • Patent number: 6534347
    Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: March 18, 2003
    Assignee: Intersil Corporation
    Inventors: Jun Zeng, Gary Mark Dolry, Praveen MurAleedharan
  • Patent number: 6362026
    Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: March 26, 2002
    Assignee: Intersil Americas Inc.
    Inventors: Jun Zeng, Gary Mark Dolry, Praveen MurAleedharan
  • Publication number: 20010050369
    Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.
    Type: Application
    Filed: March 23, 2001
    Publication date: December 13, 2001
    Applicant: INTERSIL CORPORATION
    Inventors: Jun Zeng, Gary Mark Dolry, Praveen MurAleedharan
  • Publication number: 20010007369
    Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.
    Type: Application
    Filed: February 23, 2001
    Publication date: July 12, 2001
    Inventors: Jun Zeng, Gary Mark Dolry, Praveen Shenoy MurAleedharan
  • Patent number: 6242784
    Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: June 5, 2001
    Assignee: Intersil Corporation
    Inventors: Jun Zeng, Gary Mark Dolry, Praveen MurAleedharan