Patents by Inventor Gary McAlpine
Gary McAlpine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7733770Abstract: A source node receives related frames of data to be transmitted from the source node to a destination node and places the frames in a queue. The queue is associated with a communication path over which the related frames are to be transmitted to the destination node. An interface that couples the source node to the communication path receives an indication directed to the source node of traffic congestion in the communication path. In response, the source node controls the rate at which the related frames of data are transferred from the queue to a transmit buffer accessible to the interface, in order to relieve the traffic congestion in the communication path.Type: GrantFiled: April 25, 2005Date of Patent: June 8, 2010Assignee: Intel CorporationInventors: Gary McAlpine, Tanmay Gupta, Manoj Wadekar
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Publication number: 20090073882Abstract: A node uses a two dimensional array of transmit queues to store frames to be transmitted from the node to another node. The size of the array is governed by the number of directions to which the other node may forward frames once received from the node, and the number of priorities that may be associated with the frames. The transmit queues are distinguished from each other based on direction and priority. A transmitter transmits frames dequeued from the transmit queues to the other node. Control logic that controls the transmit queues receives an indication from the other node whether the other node is experiencing traffic congestion in any of the directions and the priority of frames at or below which the control logic is to control the dequeuing of frames from transmit queues corresponding to the directions in which the other node is experiencing traffic congestion.Type: ApplicationFiled: November 21, 2008Publication date: March 19, 2009Applicant: Intel CorporationInventors: Gary McAlpine, Tanmay Gupta, Manoj K. Wadekar
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Patent number: 7457245Abstract: A node uses a two dimensional array of transmit queues to store frames to be transmitted from the node to another node. The size of the array is governed by the number of directions to which the other node may forward frames once received from the node, and the number of priorities that may be associated with the frames. The transmit queues are distinguished from each other based on direction and priority. A transmitter transmits frames dequeued from the transmit queues to the other node. Control logic that controls the transmit queues receives an indication from the other node whether the other node is experiencing traffic congestion in any of the directions and the priority of frames at or below which the control logic is to control the dequeuing of frames from transmit queues corresponding to the directions in which the other node is experiencing traffic congestion.Type: GrantFiled: September 30, 2004Date of Patent: November 25, 2008Assignee: Intel CorporationInventors: Gary McAlpine, Tanmay Gupta, Manoj K. Wadekar
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Publication number: 20070230369Abstract: An input port of a switch in a network receives a discover packet specifying an address of an endpoint in the network, selects one of a spanning-tree-protocol (STP) route or an alternate route from the switch to the endpoint, and forwards the discover packet to an output port of the switch corresponding to the selected route.Type: ApplicationFiled: March 31, 2006Publication date: October 4, 2007Inventor: Gary McAlpine
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Publication number: 20070153683Abstract: A system and method for controlling a rate of transmitting data packets into a subnet path by generating at an ingress point to the subnet a rate control signal based on a congestion level feedback signal received from the path and transmitting data packets from the ingress point into the subnet path at the rate based on the rate control signal.Type: ApplicationFiled: February 14, 2006Publication date: July 5, 2007Inventor: Gary McAlpine
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Publication number: 20070058532Abstract: According to one embodiment of the invention, a method comprises measuring traffic congestion experienced by a message transmitted from a source device, and if the measured traffic congestion exceeds a threshold limit, altering at least one bit within a Layer 2 (L2) header of the message. This bit alteration is subsequently used to determine when to notify a source of the message that the message experienced traffic congestion.Type: ApplicationFiled: September 15, 2005Publication date: March 15, 2007Inventors: Manoj Wadekar, Gary McAlpine, Tanmay Gupta
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Publication number: 20060104298Abstract: A source node receives related frames of data to be transmitted from the source node to a destination node and places the frames in a queue. The queue is associated with a communication path over which the related frames are to be transmitted to the destination node. An interface that couples the source node to the communication path receives an indication directed to the source node of traffic congestion in the communication path. In response, the source node controls the rate at which the related frames of data are transferred from the queue to a transmit buffer accessible to the interface, in order to relieve the traffic congestion in the communication path.Type: ApplicationFiled: April 25, 2005Publication date: May 18, 2006Inventors: Gary McAlpine, Tanmay Gupta, Manoj Wadekar
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Publication number: 20060072563Abstract: In general, the disclosure describes a variety of techniques that can enhance packet processing operations.Type: ApplicationFiled: October 5, 2004Publication date: April 6, 2006Inventors: Greg Regnier, Vikram Saletore, Gary McAlpine, Ram Huggahalli, Ravishankar Iyer, Ramesh Illikkal, David Minturn, Donald Newell, Srihari Makineni
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Publication number: 20060053117Abstract: A node uses a two dimensional array of transmit queues to store frames to be transmitted from the node to another node. The size of the array is governed by the number of directions to which the other node may forward frames once received from the node, and the number of priorities that may be associated with the frames. The transmit queues are distinguished from each other based on direction and priority. A transmitter transmits frames dequeued from the transmit queues to the other node. Control logic that controls the transmit queues receives an indication from the other node whether the other node is experiencing traffic congestion in any of the directions and the priority of frames at or below which the control logic is to control the dequeuing of frames from transmit queues corresponding to the directions in which the other node is experiencing traffic congestion.Type: ApplicationFiled: September 30, 2004Publication date: March 9, 2006Inventors: Gary McAlpine, Tanmay Gupta, Manoj Wadekar
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Publication number: 20050144422Abstract: A virtual to physical address translator in which a requesting process supplements a virtual memory address with a shortcut to a physical address associated with one level of a multi-level virtual address translation table. A second process, such as an I/O process, receives the shortcut and the virtual address and uses an address translator to determine the physical address. In some implementations, the shortcut may be made opaque to the requesting process such that the requesting process cannot determine the physical address represented in the shortcut.Type: ApplicationFiled: December 30, 2003Publication date: June 30, 2005Inventors: Gary McAlpine, Dave Minturn, Greg Regnier, Frank Berry
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Publication number: 20050138622Abstract: A method and apparatus for handling multiple processing streams in parallel on a single thread of a processing device. In one embodiment, a parallel processing agent includes a scheduler that multiplexes a number of processing streams, or pipelines, on a single thread of execution.Type: ApplicationFiled: December 18, 2003Publication date: June 23, 2005Inventors: Gary McAlpine, Dave Minturn
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Patent number: 6011798Abstract: An adaptive rate control scheduler multiplexes virtual circuit data stream elements for transmission onto a network from a network node. The rate control scheduler is an adaptive circuit that utilizes a schedule table (having multiple time windows) and a set of virtual circuit (VC) specific rate control parameters to supply a transmit controller with a stream of tokens (each of which represents an active VC). The order in which tokens are supplied to the transmit controller is based upon their respective time slot locations in the schedule table. Each time a token is processed by the transmit scheduler, a target time for the next processing of the VC represented by the token is calculated, based upon the stored VC-specific parameters. The token is then inserted into the schedule table in the nearest available time slot to the calculated target time. Included in the calculation of the next target time for a particular token is a gain function based upon an accumulated error value for the associated VC.Type: GrantFiled: August 15, 1997Date of Patent: January 4, 2000Assignee: Intel CorporationInventor: Gary McAlpine
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Patent number: 4837785Abstract: A data transfer system with improved data transfer efficiency is provided. The system consists of a data interchange bus having two data transfer signal paths, an address signal path, and a plurality of control signal paths. Data interchange adapters and memory interchange adapters are coupled to the bus for transferring data thereover. A data interchange adapter transfers data on the first data signal path to another data interchange adapter or to a memory interchange adapter for storage in a memory device. A memory interchange adapter transfers data obtained from a memory device on the second data signal path to a data interchange adapter. Data transfers on the two data signal paths may be made simultaneously. Data transfers on both data signal paths are made synchronously.Type: GrantFiled: June 14, 1983Date of Patent: June 6, 1989Assignee: Aptec Computer Systems, Inc.Inventor: Gary McAlpine