Abstract: A converged network adapter in sleep mode can allow a management entity to access and alter configuration of the network adapter over the network. Configuration data such as configuration parameters, firmware, and other data related to the network adapter can be stored in a memory, which can be coupled to a portion of the adapter that receives power during sleep mode. The management entity can send configuration messages to the adapter, which messages can include commands or instructions to read or write contents of the memory. The messages can include values of the configuration parameters to be altered, firmware code, etc. The management entity can also send configuration messages to a baseboard management controller (BMC) coupled to the adapter for message validation. The adapter and the BMC can send results of memory operations back to the management entity in response messages.

Abstract: A converged network adapter in sleep mode can allow a management entity to access and alter configuration of the network adapter over the network. Configuration data such as configuration parameters, firmware, and other data related to the network adapter can be stored in a memory, which can be coupled to a portion of the adapter that receives power during sleep mode. The management entity can send configuration messages to the adapter, which messages can include commands or instructions to read or write contents of the memory. The messages can include values of the configuration parameters to be altered, firmware code, etc. The management entity can also send configuration messages to a baseboard management controller (BMC) coupled to the adapter for message validation. The adapter and the BMC can send results of memory operations back to the management entity in response messages.

Abstract: A delay line calibration circuit and method are provided in which a programmable master delay line drives a delay clock and has a propagation delay that is a function of a delay setting. A delay counter is clocked by the delay clock and has a delay count. A reference counter is clocked by a reference clock and has a reference count. A control circuit controls the delay and reference counters, compares a representation of the delay count to a representation of the reference count and responsively generates a modified value for the delay setting to reduce a difference between the representations of delay count and the reference count.

Abstract: A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries.

Abstract: Method, system and signal bearing medium for configuring an integrated circuit are provided. One embodiment provides a method for configuring an integrated circuit, comprising: providing a user interface for displaying one or more abstract data elements for user selection, wherein the one or more abstract data elements represent one or more controls associated with characteristics of the integrated circuit; receiving a user selection of an abstract data element; validating associated abstract rules for the user selected abstract data element; and validating product rules for the one or more product data elements associated with the user selected abstract data element, wherein the one or more product data elements represent one or more controllable features of the integrated circuit.

Abstract: Method, system and signal bearing medium for configuring an integrated circuit are provided. One embodiment provides a method for configuring an integrated circuit, comprising: providing a user interface for displaying one or more abstract data elements for user selection, wherein the one or more abstract data elements represent one or more controls associated with characteristics of the integrated circuit; receiving a user selection of an abstract data element; validating associated abstract rules for the user selected abstract data element; and validating product rules for the one or more product data elements associated with the user selected abstract data element, wherein the one or more product data elements represent one or more controllable features of the integrated circuit.