Abstract: A packaged semiconductor chip includes a semiconductor sub strate having formed thereon: radio-frequency (RF) input and output contact pads, DC contact pads, and first and second amplifier stages. An input of the first amplifier stage is coupled with the RF input contact pad. An input and an output of the second amplifier stage are respectively coupled to an output of the first amplifier stage and the RF output contact pad. The DC contact pads and the input of the first amplifier stages are connected via an input bias coupling path. The outputs of the amplifier stages are connected via an output bias coupling path. The chip further includes a lead frame having RF input and output pins electrically coupled to the RF input and output contact pads, and input bias pins electrically coupled to the DC contact pad.

Abstract: A packaged semiconductor chip includes a power amplifier die including a semiconductor substrate, and an input contact pad, an output contact pad, first and second direct-current (DC) contact pads, one or more transistors having an input coupled to the input contact pad, and an input bias coupling path electrically coupling the first DC contact pad to the second DC contact pad and the input contact pad implemented on the semiconductor substrate. The chip further includes a lead frame having one or more radio-frequency input pins electrically coupled to the input contact pad, one or more radio-frequency output pins electrically coupled to the output contact pad, and first and second input bias pins electrically coupled to the first and second DC contact pads, respectively.

Abstract: An integrated circuit including a capacitance multiplier having reduced parasitics and injected noise compared to conventional multiplier methods. The integrated circuit includes a reference capacitor and a current mirror arrangement coupled to the reference capacitor. The current mirror arrangement, which includes a current gain factor N, varies the capacitance of the reference capacitor by a factor of N+1, based on the reference capacitor current. The current mirror arrangement includes an operational amplifier operating in conjunction with two mirror transistors to form a current mirror arrangement having little or no series resistance. The current mirror also can include a plurality of resistors configured to reduce the noise from the capacitance multiplier, thus making the capacitance multiplier useful for applications that may require relatively low noise.

Abstract: An integrated circuit including a capacitance multiplier having reduced parasitics and injected noise compared to conventional multiplier methods. The integrated circuit includes a reference capacitor and a current mirror arrangement coupled to the reference capacitor. The current mirror arrangement, which includes a current gain factor N, varies the capacitance of the reference capacitor by a factor of N+1, based on the reference capacitor current. The current mirror arrangement includes an operational amplifier operating in conjunction with two mirror transistors to form a current mirror arrangement having little or no series resistance. The current mirror also can include a plurality of resistors configured to reduce the noise from the capacitance multiplier, thus making the capacitance multiplier useful for applications that may require relatively low noise.

Abstract: An integrated circuit including a tunable capacitance multiplier. The integrated circuit includes a reference capacitor and a current source arrangement coupled in parallel to the reference capacitor. The current source arrangement can include a plurality of current sources that are switchably coupled to the reference capacitor in a manner that causes the capacitance of the reference capacitor to vary based on which current sources are coupled thereto. The current sources can be current mirror arrangements of other suitable current sources. The gain factors of the current sources are configured to establish the capacitance variability range and the incremental variance steps therein. In phase-locked loop (PLL) applications, the tunable capacitance multiplier is used to replace the main loop filter capacitor to provide a variable loop bandwidth, thus allowing relatively large values of capacitance to be realized using a relatively small physical capacitor.

Abstract: An amplifier protector and method for preventing power overload of a power amplifier and destruction of transmission circuitry and printed wiring board. The protector continually monitors the peak forward and reflected voltages of the transmitter output which are proportional to the forward and reflected power. An associated processor determines whether the forward voltage is below a threshold voltage which indicates a circuit malfunction. If the circuit malfunction is detected, the processor via an automatic level control circuit turns off the power amplifier in a timely fashion to prevent damage to the transmission circuitry.