Abstract: A semiconductor device includes an integrated circuit (IC) die including a substrate, and a plurality of through substrate via (TSV) that extends through the substrate to a protruding integral tip and which is partially covered with a dielectric liner and partially exposed from the dielectric liner. A metal layer is on the bottom surface of the IC die physically connecting the plurality of TSVs and physically and electrically connected to connecting the first metal protruding tips of TSVs.

Abstract: A method of forming a semiconductor device includes an integrated circuit (IC) die which is provided with a substrate with surfaces. At least one through substrate via (TSV) is formed through the substrate to a protruding integral tip that includes sidewalls and a distal end. A metal layer is formed on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. Completing fabrication of at least one functional circuit including at least one ground pad on the top surface of the semiconductor, wherein the ground pad is coupled to said TSV.

Abstract: A method of forming a semiconductor device includes an integrated circuit (IC) die which is provided with a substrate with surfaces. At least one through substrate via (TSV) is formed through the substrate to a protruding integral tip that includes sidewalls and a distal end. A metal layer is formed on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. Completing fabrication of at least one functional circuit including at least one ground pad on the top surface of the semiconductor, wherein the ground pad is coupled to said TSV.

Abstract: A semiconductor device includes an integrated circuit (IC) die including a substrate, and a plurality of through substrate via (TSV) that extends through the substrate to a protruding integral tip and which is partially covered with a dielectric liner and partially exposed from the dielectric liner. A metal layer is on the bottom surface of the IC die die physically connecting the plurality of TSVs and physically and electrically connected to connecting the first metal protruding tips of TSVs.

Abstract: A semiconductor device includes an integrated circuit (IC) die including a substrate, and at least one through substrate via (TSV) that extends through the substrate to a protruding integral tip that includes sidewalls and a distal end. The protruding integral tip has a tip height between 1 and 50 ?m. A metal layer is on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. A semiconductor device can include an IC die that includes TSVs and a package substrate such as a lead-frame, where the IC die includes a metal layer and an electrically conductive die attach adhesive layer, such as a solder filled polymer wherein the solder is arranged in an electrically interconnected network, between the metal layer and the die pad of the lead-frame.

Abstract: A packaged electronic device includes a leadframe including a die pad, a first, second, and third lead pin surrounding the die pad. An IC die is assembled in a face-up configuration on the lead frame. The IC die includes a substrate having an active top surface and a bottom surface, wherein the top surface includes integrated circuitry including an input pad, an output pad, a power supply pad, and a ground pad, and a plurality of through-substrate vias (TSVs) including an electrically conductive filler material and a dielectric liner. The TSVs couple the input pad to the first lead pin, the output pad to the second lead pin, the power supply pad to a third lead pin or a portion of the die pad. A fourth TSV couples pads coupled to the ground node to the die pad or a portion of the die pad for a split die pad.

Abstract: A method used during the formation of a semiconductor device assembly can include contacting an end of a conductive bump (which can be a pillar, ball, pad, post, stud, or lead as well as other types of bumps) with a conductive powder such as a solder powder to adhere the conductive powder to the end of the bump. The powder can be flowed, for example by heating, to distribute it across the end of the bump. The flowed powder can be placed in contact with a conductive pad of a receiving substrate and can then be reflowed to facilitate electrical connection between the bump and the conductive pad.

Abstract: A semiconductor device includes an integrated circuit (IC) die including a substrate, and at least one through substrate via (TSV) that extends through the substrate to a protruding integral tip that includes sidewalls and a distal end. The protruding integral tip has a tip height between 1 and 50 ?m. A metal layer is on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. A semiconductor device can include an IC die that includes TSVs and a package substrate such as a lead-frame, where the IC die includes a metal layer and an electrically conductive die attach adhesive layer, such as a solder filled polymer wherein the solder is arranged in an electrically interconnected network, between the metal layer and the die pad of the lead-frame.

Abstract: A packaged electronic device includes a leadframe including a die pad, a first, second, and third lead pin surrounding the die pad. An IC die is assembled in a face-up configuration on the lead frame. The IC die includes a substrate having an active top surface and a bottom surface, wherein the top surface includes integrated circuitry including an input pad, an output pad, a power supply pad, and a ground pad, and a plurality of through-substrate vias (TSVs) including an electrically conductive filler material and a dielectric liner. The TSVs couple the input pad to the first lead pin, the output pad to the second lead pin, the power supply pad to a third lead pin or a portion of the die pad. A fourth TSV couples pads coupled to the ground node to the die pad or a portion of the die pad for a split die pad.

Abstract: Semiconductor chip (1101) of a ball grid array device (1100) is mounted onto tape substrate (1102) using attach adhesive (1103). The metal layer on the top surface of substrate (1102) uses between about 30% to 90% of its area for connecting lines (1104), and only the remainder for members/rings (1105) and terminals (1106). Routing of differential pair signals and large numbers of signals on a single layer tape package are feasible. This embodiment creates an inexpensive high performance tape ball grid array package for chip-scale devices. Terminals (1106) serve the connection (by bonding wires or reflow bumps) to the chip contact pads. Inserted in members/rings (1105) are the conductive pins (1107), which serve as anchors for the solder bodies/balls (1108). Pins (1107) are substantially insensitive to the thermomechanical stresses, which occur in device (1100) during assembly, testing and operation.

Abstract: A method used during the formation of a semiconductor device assembly can include contacting an end of a conductive bump (which can be a pillar, ball, pad, post, stud, or lead as well as other types of bumps) with a conductive powder such as a solder powder to adhere the conductive powder to the end of the bump. The powder can be flowed, for example by heating, to distribute it across the end of the bump. The flowed powder can be placed in contact with a conductive pad of a receiving substrate and can then be reflowed to facilitate electrical connection between the bump and the conductive pad.

Abstract: Semiconductor chip (1101) of a ball grid array device (1100) is mounted onto tape substrate (1102) using attach adhesive (1103). The metal layer on the top surface of substrate (1102) uses between about 30% to 90% of its area for connecting lines (1104), and only the remainder for members/rings (1105) and terminals (1106). Routing of differential pair signals and large numbers of signals on a single layer tape package are feasible. This embodiment creates an inexpensive high performance tape ball grid array package for chip-scale devices. Terminals (1106) serve the connection (by bonding wires or reflow bumps) to the chip contact pads. Inserted in members/rings (1105) are the conductive pins (1107), which serve as anchors for the solder bodies/balls (1108). Pins (1107) are substantially insensitive to the thermomechanical stresses, which occur in device (1100) during assembly, testing and operation.

Abstract: A substrate (300) for use in semiconductor devices, having first (301a) and second (301b) surfaces and a base structure including insulating material. A plurality of I/O terminal pads (302, 303) is distributed on the first and second surfaces, respectively, and these terminal pads are interconnected by conducting traces integral to the base structure. A plurality of selected metal layers (304 to 309) is distributed in the structure; the metal layers are substantially parallel to the surfaces and separated by the insulating material from each other and from the surfaces. At least one metal layer (304 or 307, respectively) opposite each of the surfaces has openings (320a, 320b) therein configured so that the metal areas (307a) directly opposite each of the terminal pads (303) are electrically isolated from the remainder of the layer. The width of these openings is selected to provide a pre-determined capacitance between each of the terminals (303) and the remainder of the metal layer (307).

Abstract: A vertical stack of semiconductor devices is formed by folding a strip-like flexible interconnector assembled with integrated circuit chips, packages and/or passive components and attaching coupling members solderable to other parts (FIGS. I4A and I4B).