Abstract: Embodiments of the invention include an apparatus and method for continuously calibrating the frequency of a clock and data recovery (CDR) circuit. The apparatus includes a delay arrangement that generates a gating signal, and a gated voltage-controlled oscillator that is enabled by the gating signal. The gated voltage-controlled oscillator generates a recovered clock signal that is based on the data signal input to the CDR circuit. The apparatus also includes a frequency control loop that continuously calibrates the gated voltage-controlled oscillator in such a way that the frequency of the clock signal generated by the gated voltage-controlled oscillator continues to be one half of the period of the data bits in the input data signal and the clock signal remains synchronized to the center of the data state transitions of the input data signal. Alternatively, a secondary frequency control loop adjusts the amount of delay in the frequency control loop.

Abstract: A direct calibration technique significantly tightens a tolerance band between multiple voltage controlled oscillators (VCOs), to correct for slight frequency mismatch between the multiple VCOs. The tightened tolerance band enhances the bit error rate (BER) and/or lengthens the possible consecutive identical digits (CIDs) length, and is particularly useful in integrated circuit applications. A Frequency Locked Loop (FLL), an accumulator, and a DAC are implemented to form a calibration loop that becomes far more digital in nature than a PLL, permitting greater embedded circuit test coverage and ease of integration in VLSI digital technologies. A frequency calibrated loop with digital accumulator and DAC in lieu of a PLL with associated charge pump integrator eliminates the need for large integrated capacitors, sensitivity to drift due to the leakage currents associated with deep sub-micron technologies, and embedded analog voltages which generally cannot be tested.

Abstract: A differential voltage-controlled oscillator (VCO) employs at least two pairs of varactors, each pair of varactors driven with a corresponding differential control voltage, to generate a differential oscillating waveform. The capacitance of each pair of varactors adds to form the total capacitance of an inductor-capacitor (LC) tank circuit of the VCO, which determines an oscillation frequency of the differential oscillating waveform of the VCO. One differential control voltage controls a capacitance of the first varactor pair for a relatively coarse adjustment of the oscillation frequency, and the other differential control voltage controls a capacitance of the second varactor pair for a relatively fine adjustment of the oscillation frequency.

Abstract: A phase-locked loop (PLL) employs a phase detector (PD) generating an up/down signal based on the phase error between a data signal and a clock signal input to the phase detector. The PD senses excess jitter and extends the loop bandwidth to accommodate such excess jitter. Phase error is derived by sampling of the clock signal and at least one phase-shifted version of the clock signal by the data signal, and a retimed data is generated by the PD by sampling of the data signal by the clock signal. The sampled clocks are employed to generate a modified control signal with greater resolution in detecting the phase error, which, in turn, increases the loop bandwidth.

Abstract: A phase detector (PD) generates an up/down signal based on the phase error between data and clock signals input to the phase detector. A voltage controlled oscillator (VCO) generates the clock signal. The up/down signal is applied to a proportional charge pump and a truncated version of the up/down signal is applied to an integral charge pump. The proportional charge pump generates a first voltage for a first time period across a resistor based on the up/down signal, while the integral charge pump generates a second voltage for a second time period across a capacitor based upon the truncated version of the up/down signal and the sampling rate of the data signal by the PD. The second time period is less than the first time period. The first and second voltages are combined and applied to the VCO to drive the clock signal to synchronization with the data.