Abstract: Systems and methods are provided for an automatic exposure detection feature for adding to an x-ray panel readout device, including an imaging panel having a low power mode, a sense circuit for receiving an input signal in the low power mode and restricting an input signal voltage to a first voltage, and a sensor for sensing a change in the input signal voltage, wherein the change in input signal voltage indicates exposure to an x-ray signal.

Abstract: Systems and methods are provided for an automatic exposure detection feature for adding to an x-ray panel readout device, including an imaging panel having a low power mode, a sense circuit for receiving an input signal in the low power mode and restricting an input signal voltage to a first voltage, and a sensor for sensing a change in the input signal voltage, wherein the change in input signal voltage indicates exposure to an x-ray signal.

Abstract: When reservoir capacitors are moved on-chip for individual bit decisions, a successive approximation register analog-to-digital converter (SAR ADC) has an addition source of error which can significantly affect the performance of the SAR ADC. Calibration techniques can be applied to measure and correct for such error in an SAR ADC using decide-and-set switching. Specifically, a calibration technique can expose the effective bit weight of each bit under test using a plurality of special input voltages and storing a calibration word for each bit under test to correct for the error. Such a calibration technique can lessen the need to store a calibration word for each possible output word to correct the additional source of error. Furthermore, another calibration technique can expose the effective bit weight of each bit under test without having to generate the plurality of special input voltages.

Abstract: The system may include a pixel array, a selector, a sampler, and a converter. The pixel array may generate output signals representing radiation incident upon the pixel array. The selector may select one of the output signals. The sampler may sample the selected output signal. The converter may generate a digital signal based upon the selected output signal. The sampler may include a charge integrator that compensates for parasitic capacitance of the selector by selecting a first feedback capacitance to obtain a first sample, and after obtaining the first sample, selecting a second feedback capacitance to obtain a second sample. The first feedback capacitance may be greater than the second feedback capacitance.

Abstract: When reservoir capacitors are moved on-chip for individual bit decisions, a successive approximation register analog-to-digital converter (SAR ADC) has an addition source of error which can significantly affect the performance of the SAR ADC. Calibration techniques can be applied to measure and correct for such error in an SAR ADC using decide-and-set switching. Specifically, a calibration technique can expose the effective bit weight of each bit under test using a plurality of special input voltages and storing a calibration word for each bit under test to correct for the error. Such a calibration technique can lessen the need to store a calibration word for each possible output word to correct the additional source of error. Furthermore, another calibration technique can expose the effective bit weight of each bit under test without having to generate the plurality of special input voltages.

Abstract: The system may include a pixel array, a selector, a sampler, and a converter. The pixel array may generate output signals that representing radiation incident upon the pixel array. The selector may select one of the output signals. The sampler may sample the selected output signal. The converter may generate a digital signal based upon the selected output signal. The sampler may include a charge integrator that compensates for parasitic capacitance of the selector by selecting a first feedback capacitance to obtain a first sample, and after obtaining the first sample, selecting a second feedback capacitance to obtain a second sample. The first feedback capacitance may be greater than the second feedback capacitance.

Abstract: A circuit system for performing correlated double sampling may include a signal sampling stage having an amplifier with a feedback capacitor and a pair of storage capacitors coupled to an output of the amplifier, and a differential analog to digital converter (ADC) having a pair of inputs coupled respectively to storage capacitors of the signal sampling stage. The signal sampling stage may receive reset and signal values from a sensor device and may store processed versions of those signals on respective storage capacitors. The differential ADC may generate a digital value representing a signal captured by the sensor device from a differential digitization operation performed on the processed versions of the reset and signal values. In this manner, the system may correct for any signal errors introduced by components of the sampling stage.

Abstract: A dual channel ADC uses two digital to analog converters (DACs) and a single comparator to convert two analog input channels. One DAC is used for successive approximation, while the other DAC is used for calibration. The dual channel ADC allows for sampling and conversion of single-ended, pseudo-differential, and fully differential analog input signals while maintaining layout symmetry and reducing crosstalk without substantially increasing circuit area. The single comparator is used for converting both analog input channels. Additional logic (such as switches or digital logic) is used to connect the input sampling capacitors and DACs to the appropriate inputs of the comparator for converting the analog input channels.

Abstract: A dual channel ADC uses two digital to analog converters (DACs) and a single comparator to convert two analog input channels. One DAC is used for successive approximation, while the other DAC is used for calibration. The dual channel ADC allows for sampling and conversion of single-ended, pseudo-differential, and fully differential analog input signals while maintaining layout symmetry and reducing crosstalk without substantially increasing circuit area. The single comparator is used for converting both analog input channels. Additional logic (such as switches or digital logic) is used to connect the input sampling capacitors and DACs to the appropriate inputs of the comparator for converting the analog input channels.