Patents by Inventor Gary R. Early

Gary R. Early has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High performance computing (HPC) node having a plurality of switch coupled processors
    Patent number: 10769088
    Abstract: A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: September 8, 2020
    Assignee: Raytheon Company
    Inventors: James D. Ballew, Gary R. Early
  • HIGH PERFORMANCE COMPUTING (HPC) NODE HAVING A PLURALITY OF SWITCH COUPLED PROCESSORS
    Publication number: 20190294576
    Abstract: A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.
    Type: Application
    Filed: April 1, 2019
    Publication date: September 26, 2019
    Inventors: James D. Ballew, Gary R. Early
  • High performance computing (HPC) node having a plurality of switch coupled processors
    Patent number: 10289586
    Abstract: A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: May 14, 2019
    Assignee: Raytheon Company
    Inventors: James D. Ballew, Gary R. Early
  • SYSTEM AND METHOD FOR CLUSTER MANAGEMENT BASED ON HPC ARCHITECTURE
    Publication number: 20160057016
    Abstract: Cluster management software comprises a plurality of cluster agents, with each cluster agent associated with an HPC node including an integrated fabric and the cluster agent operable to determine a status of the associated HPC node. The software further includes a cluster management engine communicably coupled with the plurality of the HPC nodes and operable to execute an HPC job using a dynamically allocated subset of the plurality of HPC nodes based on the determined status of the plurality of HPC nodes.
    Type: Application
    Filed: November 2, 2015
    Publication date: February 25, 2016
    Inventors: James D. Ballew, Gary R. Early, Shannon V. Davidson
  • HIGH PERFORMANCE COMPUTING (HPC) NODE HAVING A PLURALITY OF SWITCH COUPLED PROCESSORS
    Publication number: 20150212964
    Abstract: A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.
    Type: Application
    Filed: April 9, 2015
    Publication date: July 30, 2015
    Inventors: James D. Ballew, Gary R. Early
  • High performance computing (HPC) node having a plurality of switch coupled processors
    Patent number: 9037833
    Abstract: A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: May 19, 2015
    Assignee: RAYTHEON COMPANY
    Inventors: James D. Ballew, Gary R. Early
  • Coupling processors to each other for high performance computing (HPC)
    Patent number: 8335909
    Abstract: A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: December 18, 2012
    Assignee: Raytheon Company
    Inventors: James D. Ballew, Gary R. Early