Abstract: A chiller system including an evaporator for evaporating a refrigerant and a water pipe in fluid communication with the evaporator. The water pipe is configured to allow water to pass through at a flow rate and to circulate the water with the evaporator to exchange heat with the refrigerant in the evaporator. The chiller system includes a flow restrictor tube within the water pipe that is configured to allow the water to flow through the flow restrictor tube at a reduced flow rate relative to the flow rate. The chiller system also includes a measuring probe that passes through walls of the water pipe and the flow restrictor tube and includes an accuracy range of flow rates less than the flow rate. The measuring probe is configured to measure the reduced flow rate within the flow restrictor tube where the reduced flow rate is within the accuracy range.

Abstract: A chiller system including an evaporator for evaporating a refrigerant and a water pipe in fluid communication with the evaporator. The water pipe is configured to allow water to pass through at a flow rate and to circulate the water with the evaporator to exchange heat with the refrigerant in the evaporator. The chiller system includes a flow restrictor tube within the water pipe that is configured to allow the water to flow through the flow restrictor tube at a reduced flow rate relative to the flow rate. The chiller system also includes a measuring probe that passes through walls of the water pipe and the flow restrictor tube and includes an accuracy range of flow rates less than the flow rate. The measuring probe is configured to measure the reduced flow rate within the flow restrictor tube where the reduced flow rate is within the accuracy range.

Abstract: A reconfigurable processor array (RPA) for performing high speed operations on data arrays and eliminating I/O bottleneck. The array memory has a working side for storing arrays to be processed during a given array operation, and an I/O side for loading an array to be used during a subsequent operation and downloading an array resulting from a preceding operation.

Abstract: A block processing computing system includes a decomposition unit, a control circuit, a system memory, a data block path and a block processor. The decomposition unit receives externally-supplied primitive command packets and decomposes the primitive into machine language operations on computational blocks of data. The control circuitry generates control and address signals for performing the machine level operations. The data block path includes alignment circuitry for selecting data from burst-accessed blocks of data and a macropipeline for controllably storing and transferring blocks of data to and from the block processor. The block processor has interchangeable, double-buffered local zone memories and a parallel set of pipelined vector processors for performing block operations on computational blocks of data.