Abstract: A plurality of integrated circuit packages are disposed on a substrate. The plurality of integrated circuit packages includes a first type of integrated circuit package that has an inactive side facing the substrate and an active side facing away from the substrate. The plurality of integrated circuit packages also includes a second type of integrated circuit package that has an inactive side facing away from the substrate and an active side facing the substrate. The first type of integrated circuit package and the second type of integrated circuit package are disposed such that a proximity communication enabled portion of the first type of integrated circuit package is aligned with a proximity communication enabled portion of the second type of integrated circuit package.

Abstract: One embodiment of the present invention provides a proximity I/O switch, which is configured to transfer data between the components in a computer system. This proximity I/O switch is comprised of multiple switch chips, which are coupled together through capacitive coupling. This enables the multiple switch chips to communicate with each other without being constrained by the limitations of conventional non-capacitive communication mechanisms. The multiple switch chips in the proximity I/O switch are also configured to communicate with components in the computer system through conventional non-capacitive communication mechanisms.

Abstract: One embodiment of the present invention provides a proximity I/O switch, which is configured to transfer data between the components in a computer system. This proximity I/O switch is comprised of multiple switch chips, which are coupled together through capacitive coupling. This enables the multiple switch chips to communicate with each other without being constrained by the limitations of conventional non-capacitive communication mechanisms. The multiple switch chips in the proximity I/O switch are also configured to communicate with components in the computer system through conventional non-capacitive communication mechanisms.

Abstract: One embodiment of the present invention provides an integrated circuit assembly module, including a first semiconductor die and a second semiconductor die, each semiconductor die with an active face upon which active circuitry and signal pads reside and a back face opposite the active face. The first and second semiconductor dies are positioned face-to-face within the assembly module so that signal pads on the first semiconductor die overlap with signal pads on the second semiconductor die, thereby facilitating capacitive communication between the first and second semiconductor dies. Additionally, the first and second semiconductor dies are pressed together between a first substrate and a second substrate so that a front side of the first substrate is in contact with the back face of the first semiconductor die and a front side of the second substrate is in contact with the back face of the second semiconductor die.

Abstract: One embodiment of the present invention provides an integrated circuit assembly module, including a first semiconductor die and a second semiconductor die, each semiconductor die with an active face upon which active circuitry and signal pads reside and a back face opposite the active face. The first and second semiconductor dies are positioned face-to-face within the assembly module so that signal pads on the first semiconductor die overlap with signal pads on the second semiconductor die, thereby facilitating capacitive communication between the first and second semiconductor dies. Additionally, the first and second semiconductor dies are pressed together between a first substrate and a second substrate so that a front side of the first substrate is in contact with the back face of the first semiconductor die and a front side of the second substrate is in contact with the back face of the second semiconductor die.

Abstract: One embodiment of the present invention provides a system to facilitate multithreading a computer processor pipeline. The system includes a pipeline that is configured to accept instructions from multiple independent threads of operation, wherein each thread of operation is unrelated to the other threads of operation. This system also includes a control mechanism that is configured to control the pipeline. This control mechanism is statically scheduled to execute multiple threads in round-robin succession. This static scheduling eliminates the need for communication between stages of the pipeline.

Abstract: A microprocessor is configured to generate help instructions in response to a data cache miss. The help instructions flow through the instruction processing pipeline of the microprocessor in a fashion similar to the instruction which caused the miss (the "miss instruction"). The help instructions use the source operands of the miss instruction to form the miss address, thereby providing the fill address using the same elements which are used to calculate cache access addresses. In one embodiment, a fill help instruction and a bypass help instruction are generated. The fill help instruction provides the input address to the data cache during the clock cycle in which the fill data arrives. The appropriate row of the data cache is thereby selected for storing the fill data. The bypass help instruction is dispatched to arrive in a second pipeline stage different from the stage occupied by the fill help instruction.

Abstract: A CPU (central processing unit) of a computer. The CPU comprises a dispatch controller, a pipeline, a working register file, and an architectural register file. The dispatch controller dispatches instructions for execution and determines whether the dispatched instructions are valid or invalid. The pipeline executes the dispatched instructions using selected operands in the pipeline and generates operands in response. The working register file stores the generated operands before the executed instructions are determined to be valid or invalid by the dispatch controller such that the stored operands may be subsequently selected for use in executing an instruction in the pipeline. The architectural register file stores the generated operands for those of the executed instructions that are determined to be valid by the dispatch controller and transfer operands currently stored therein when one of the executed instructions is determined to be invalid by the dispatch logic.

Abstract: A CPU (central processing unit) of a computer that comprises an issue unit and an execution unit. The issue unit selectively issues arithmetic instructions of a predefined arithmetic instruction type as performance critical arithmetic instructions and non-performance critical arithmetic instructions. The execution unit comprises a performance critical pipeline to execute the performance critical arithmetic instructions. The execution unit also comprises a non-performance critical pipeline to execute the non-performance critical arithmetic instructions.

Abstract: A microprocessor is configured to generate help instructions in response to a data cache miss. The help instructions flow through the instruction processing pipeline of the microprocessor in a fashion similar to the instruction which caused the miss (the "miss instruction"). The help instructions use the source operands of the miss instruction to form the miss address, thereby providing the fill address using the same elements which are used to calculate cache access addresses. In one embodiment, a fill help instruction and a bypass help instruction are generated. The fill help instruction provides the input address to the data cache during the clock cycle in which the fill data arrives. The appropriate row of the data cache is thereby selected for storing the fill data. The bypass help instruction is dispatched to arrive in a second pipeline stage different from the stage occupied by the fill help instruction.

Abstract: A significant reduction in the latency between the time the addressed components of memory are ready and the time addressed data is available to the address components of memory is achieved by processing the raw address information faster than the addition used in the prior art. XOR memory addressing replaces the addition of the base and offset address components with an XOR operation, eliminating carry propagation and reducing overall latency. In another embodiment, a sum-addressed memory (SAM) also eliminates the carry propagation and thus reduce the latency while providing the correct base+offset index to access the memory word line corresponding to the correct addition; thus a SAM causes no XOR duplicate problems.

Abstract: The disclosed method of designing a circuit includes the step of building a dependency graph for a set of computer program instructions. A set of artificial dependencies are inserted into the dependency graph to form a modified dependency graph. The artificial dependencies are hardware limitations such as register renaming limitations, branch prediction limitations, and memory disambiguation limitations. The execution performance of selected artificial dependencies of the modified dependency graph are then analyzed to generate a set of performance values. The top-ranked performance value is associated with a modified dependency graph with a selected set of hardware dependencies. A circuit specification corresponding to the modified dependency graph with the selected set of hardware dependencies is then used to fabricate a circuit.

Abstract: Disclosed herein is an automatically controlled weigh feeding apparatus including a container for prefilling with a substance, a device for discharging the substance from the container at a controllable rate, apparatus for weighing the substance being discharged and for producing an electrical signal proportional to that weight, a voltage to frequency converter connected to receive the electrical signals, a digital computer, apparatus coupled to an output of the voltage to frequency converter for inputting data signals to the digital computer, the computer being adapted to compute a corrective signal based on the input data signals received, and coupling apparatus coupled between the computer and the device for discharging the substance from the container for controlling the rate of discharge responsive to the corrective signal.

Abstract: Disclosed herein is an automatically controlled weigh feeding apparatus including a container for prefilling with a substance, a device for discharging the substance from the container at a controllable rate, apparatus for weighing the substance being discharged and for producing an electrical signal proportional to that weight, a voltage to frequency converter connected to receive the electrical signals, a digital computer, apparatus coupled to an output of the voltage to frequency converter for inputting data signals to the digital computer, the computer being adapted to compute a corrective signal based on the input data signals received, and coupling apparatus coupled between the computer and the device for discharging the substance from the container for controlling the rate of discharge responsive to the corrective signal.

Abstract: Disclosed herein is an automatically controlled weigh feeding apparatus including a container for prefilling with a substance, a device for discharging the substance from the container at a controllable rate, apparatus for weighing the substance being discharged and for producing an electrical signal proportional to that weight, a voltage to frequency converter connected to receive the electrical signals, a digital computer, apparatus coupled to an output of the voltage to frequency converter for inputting data signals to the digital computer, the computer being adapted to compute a corrective signal based on the input data signals received, and coupling apparatus coupled between the computer and the device for discharging the substance from the container for controlling the rate of discharge responsive to the corrective signal.