Abstract: A high speed parallel digital adder/subtracter employing a specially chosen combination of "conditional" and "look-ahead" approaches which permits economically achieving high speed operation even for input operands containing relatively large numbers of digits. In a preferred embodiment, simultaneously produced look-ahead carry and carry-not signals are generated and employed to select particular ones of simultaneously generated conditional sums for one or more operand digits so as to simultaneously provide resulting digital sums which properly represent the sum of the input operands.