Abstract: The present invention solves the problems associated with the prior art by providing a latency prediction bit (LPB) to indicate the latency with which an instruction should be executed, implicitly indicating whether a data dependency is likely to exist and the likelihood of that dependency causing a hazard. In a processor according to the present invention, an instruction dependent upon a given LDI instruction is issued a given number of machine cycles after that LDI instruction, the number of machine cycles being based on the value of the LPB associated with that LDI instruction. The LPB's value, in turn, depends on whether data will need to be forwarded to the functional unit involved during the execution of LDI instruction. The ability to predict such hazards is important in maintaining a pipeline's throughput and avoiding unnecessary recirculations.

Abstract: An apparatus for executing an instruction is provided. The instruction loads data into one of a plurality of registers in a register file and is in a first group of instructions. A second group of instructions is executed sequentially after the first group of instructions. The first and second groups of instructions should each include at least one instruction. The apparatus includes a first memory, a second memory, a first functional unit coupled to the first memory, and a second functional unit coupled to the first memory and to the second memory. The first and second functional units are both capable of executing the instruction. Also included is an instruction issue unit coupled to the first and the second functional units. The instruction issue unit issues the instruction to a selected functional unit selected from one of the first and the second functional units. This selection is based on a load prediction bit associated with the instruction.