Abstract: An architecture for a post regulator control circuit that utilizes an advance trigger signal to trigger the post regulator ramp. This advance trigger signal anticipates the beginning and end of a power cycle, and can be used to drive all of the secondary rectifier switches with optimal timing to minimize both cross conduction and body diode conduction. The architecture can be used to cascade an arbitrary number of post regulators. The present invention provides to the auxiliary outputs the full range of regulation available to the main output even in light load conditions. Rather than sensing the beginning or end of the power cycle, the present invention anticipates the beginning and end of the power cycle using the pulse train generated by the feedback loop for the main output. This allows the circuit to prepare the switches for the beginning of the power cycle and avoids problems encountered with inherent propagation delays in the circuit.