Abstract: An integrated circuit and method for testing memory on the integrated circuit are provided. The integrated circuit has processing logic for performing data processing operations on data, and a plurality of memory units for storing data for access by the processing logic. Further, memory test logic is provided to perform a sequence of tests in order to seek to detect memory defects in the memory units. The memory test logic comprises a plurality of test wrapper units, each test wrapper unit associated with one of the memory units and being operable to execute tests on the associated memory unit, and a test controller for controlling performance of the sequence of tests by communicating with each of the test wrapper units to provide test data defining each test to be executed by that test wrapper unit.

Abstract: The application discloses an integrated circuit comprising: circuitry; a fusebox for storing an array of data identifying faulty elements within said circuitry; at least one fusebox controller for repairing said faulty elements in said circuitry in response to data received from said fusebox; a data communication path linking said fusebox controller with said fusebox; wherein said data stored in said fusebox is compacted data and said at least one fusebox controller comprises a data expander for expanding said compacted data received from said fusebox via said data communication path prior to repairing any faulty elements in said circuitry.

Abstract: A memory is disclosed comprising: a storage array for storing data; and access circuitry for transmitting data to and from the storage array. The access circuitry forms a data path for inputting and outputting data to the storage array. The access circuitry comprises a latch configured to latch in response to a first phase of a first clock signal and a further latch configured to latch in response to a second phase of a second clock signal, the further latch comprises an output latch for outputting the data from the storage array, and the first and second clock signals are synchronized with each other.

Abstract: A memory is disclosed comprising: a storage array for storing data; and access circuitry for transmitting data to and from the storage array. The access circuitry forms a data path for inputting and outputting data to the storage array. The access circuitry comprises a latch configured to latch in response to a first phase of a first clock signal and a further latch configured to latch in response to a second phase of a second clock signal, the further latch comprises an output latch for outputting the data from the storage array, and the first and second clock signals are synchronised with each other.

Abstract: An integrated circuit 2 includes a plurality of circuit blocks 38, 40, 44 each having an associated serial scan chain loop 32, 34, 36 which extends from a converter 10, to the circuit block 38, 42, 44 in question and then back to the converter 10. Multiplexing circuitry 50, 52 associated with each serial scan chain loop 32, 34, 36 is used to either include that serial scan chain loop 32, 34, 36 in a combined serial scan chain or to bypass that serial scan chain loop 32, 34, 36. The circuit blocks 38, 42, 44 may be bypassed in this way if they are defective or if they are powered-down.

Abstract: The application discloses an integrated circuit comprising: circuitry; a fusebox for storing an array of data identifying faulty elements within said circuitry; at least one fusebox controller for repairing said faulty elements in said circuitry in response to data received from said fusebox; a data communication path linking said fusebox controller with said fusebox; wherein said data stored in said fusebox is compacted data and said at least one fusebox controller comprises a data expander for expanding said compacted data received from said fusebox via said data communication path prior to repairing any faulty elements in said circuitry.

Abstract: An integrated circuit 2 includes a plurality of circuit blocks 38, 40, 44 each having an associated serial scan chain loop 32, 34, 36 which extends from a converter 10, to the circuit block 38, 42, 44 in question and then back to the converter 10. Multiplexing circuitry 50, 52 associated with each serial scan chain loop 32, 34, 36 is used to either include that serial scan chain loop 32, 34, 36 in a combined serial scan chain or to bypass that serial scan chain loop 32, 34, 36. The circuit blocks 38, 42, 44 may be bypassed in this way if they are defective or if they are powered-down.