Patents by Inventor Gary Robertson
Gary Robertson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11522528Abstract: This application relates to methods and apparatus for voltage control, and in particular to maintain safe voltages for components of audio driving circuits that are operable in a high voltage mode. An audio driving circuit (100) may include a power supply module (106) and may be operable such that, in use, a voltage magnitude at a source terminal of at least a first transistor (306, 309, 603, 605) of the audio driving circuit can exceed its gate-source voltage tolerance. A voltage generator (111 P) is configured to output a first intermediate voltage (VSAFEP) to an intermediate voltage path for use as a gate control voltage for at least the first transistor, to maintain its gate-source voltage below tolerance. An intermediate path voltage clamp (114P) is provided for selectively clamping the intermediate voltage path to a voltage level, so as to maintain the magnitude of the gate-source voltage of the first transistor below tolerance.Type: GrantFiled: November 2, 2020Date of Patent: December 6, 2022Assignee: Cirrus Logic, Inc.Inventors: Gary Robertson, Hamed Sadati, Rupesh Khare, Sameer Baveja
-
Publication number: 20210075404Abstract: This application relates to methods and apparatus for voltage control, and in particular to maintain safe voltages for components of audio driving circuits that are operable in a high voltage mode. An audio driving circuit (100) may include a power supply module (106) and may be operable such that, in use, a voltage magnitude at a source terminal of at least a first transistor (306, 309, 603, 605) of the audio driving circuit can exceed its gate-source voltage tolerance. A voltage generator (111 P) is configured to output a first intermediate voltage (VSAFEP) to an intermediate voltage path for use as a gate control voltage for at least the first transistor, to maintain its gate-source voltage below tolerance. An intermediate path voltage clamp (114P) is provided for selectively clamping the intermediate voltage path to a voltage level, so as to maintain the magnitude of the gate-source voltage of the first transistor below tolerance.Type: ApplicationFiled: November 2, 2020Publication date: March 11, 2021Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Gary ROBERTSON, Hamed SADATI, Rupesh KHARE, Sameer BAVEJA
-
Patent number: 10855258Abstract: This application relates to methods and apparatus for voltage control, and in particular to maintain safe voltages for components of audio driving circuits that are operable in a high voltage mode. An audio driving circuit (100) may include a power supply module (106) and may be operable such that, in use, a voltage magnitude at a source terminal of at least a first transistor (306, 309, 603, 605) of the audio driving circuit can exceed its gate-source voltage tolerance. A voltage generator (111P) is configured to output a first intermediate voltage (VSAFEP) to an intermediate voltage path for use as a gate control voltage for at least the first transistor, to maintain its gate-source voltage below tolerance. An intermediate path voltage clamp (114P) is provided for selectively clamping the intermediate voltage path to a voltage level, so as to maintain the magnitude of the gate-source voltage of the first transistor below tolerance.Type: GrantFiled: October 7, 2019Date of Patent: December 1, 2020Assignee: Cirrus Logic, Inc.Inventors: Gary Robertson, Hamed Sadati, Rupesh Khare, Sameer Baveja
-
Publication number: 20140375775Abstract: Systems and methods for 2D image and spatial data capture for 3D stereo imaging are disclosed. The system utilizes a cinematography camera and at least one reference or “witness” camera spaced apart from the cinematography camera at a distance much greater that the interocular separation to capture 2D images over an overlapping volume associated with a scene having one or more objects. The captured image data is post-processed to create a depth map, and a point cloud is created form the depth map. The robustness of the depth map and the point cloud allows for dual virtual cameras to be placed substantially arbitrarily in the resulting virtual 3D space, which greatly simplifies the addition of computer-generated graphics, animation and other special effects in cinemagraphic post-processing.Type: ApplicationFiled: September 10, 2014Publication date: December 25, 2014Inventors: Hoyt H. Yeatman, JR., Gary Robertson
-
Patent number: 8867827Abstract: Systems and methods for 2D image and spatial data capture for 3D stereo imaging are disclosed. The system utilizes a cinematography camera and at least one reference or “witness” camera spaced apart from the cinematography camera at a distance much greater that the interocular separation to capture 2D images over an overlapping volume associated with a scene having one or more objects. The captured image data is post-processed to create a depth map, and a point cloud is created form the depth map. The robustness of the depth map and the point cloud allows for dual virtual cameras to be placed substantially arbitrarily in the resulting virtual 3D space, which greatly simplifies the addition of computer-generated graphics, animation and other special effects in cinemagraphic post-processing.Type: GrantFiled: November 25, 2013Date of Patent: October 21, 2014Assignee: Shapequest, Inc.Inventors: Hoyt H. Yeatman, Jr., Gary Robertson
-
Publication number: 20140098199Abstract: Systems and methods for 2D image and spatial data capture for 3D stereo imaging are disclosed. The system utilizes a cinematography camera and at least one reference or “witness” camera spaced apart from the cinematography camera at a distance much greater that the interocular separation to capture 2D images over an overlapping volume associated with a scene having one or more objects. The captured image data is post-processed to create a depth map, and a point cloud is created form the depth map. The robustness of the depth map and the point cloud allows for dual virtual cameras to be placed substantially arbitrarily in the resulting virtual 3D space, which greatly simplifies the addition of computer-generated graphics, animation and other special effects in cinemagraphic post-processing.Type: ApplicationFiled: November 25, 2013Publication date: April 10, 2014Applicant: ShapeQuest, Inc.Inventors: Hoyt H. Yeatman, JR., Gary Robertson
-
Publication number: 20110222757Abstract: Systems and methods for 2D image and spatial data capture for 3D stereo imaging are disclosed. The system utilizes a cinematography camera and at least one reference or “witness” camera spaced apart from the cinematography camera at a distance much greater that the interocular separation to capture 2D images over an overlapping volume associated with a scene having one or more objects. The captured image date is post-processed to create a depth map, and a point cloud is created form the depth map. The robustness of the depth map and the point cloud allows for dual virtual cameras to be placed substantially arbitrarily in the resulting virtual 3D space, which greatly simplifies the addition of computer-generated graphics, animation and other special effects in cinemagraphic post-processing.Type: ApplicationFiled: March 7, 2011Publication date: September 15, 2011Inventors: Hoyt H. Yeatman, JR., Gary Robertson
-
Patent number: 7247209Abstract: An apparatus and method for the improved combined edge bead removal and backside wash of spin coated semiconductor wafers is disclosed. This is preferably accomplished by providing a nozzle having a plurality of outlets adapted for the ejection of a cleaning fluid onto the backside of a semiconductor wafer. This cleaning fluid can be EEP or a similar EBR type of solvent. This dual outlet nozzle can be mounted to a stationary EBR arm, and preferably comprises two outlets located on a beveled top surface that are separated at a predetermined angle. The angle of this beveled top surface with respect to a horizontal plane of the processed wafer is preferably about 45 degrees, while the angle of each nozzle outlet with respect to a primary axis of the stationary EBR arm is also preferably about 45 degrees. Other angles are also possible in order to maximize solvent jet efficiency.Type: GrantFiled: June 12, 2003Date of Patent: July 24, 2007Assignee: National Semiconductor CorporationInventors: Gary Robertson, Robert Boyd Finlay
-
Patent number: 7171893Abstract: A rotary press is supported on a frame allowing liquid and solid receivers to be placed underneath the rotary press. The rotary press has an outer ring and an inner drum. The inner drum has an upper and lower flange with a stripper ring retained between these flanges. The flanges form two sides of the cavity where the pressing takes place. The flanges carry the solids away from the pressing zone to a discharge zone where the stripper ring expels the solids. By transporting the solids away from the pressing zone where liquids are expelled, reabsorption of the liquid is avoided. The stripper ring can move relative to the two flanges and is biased against the outer ring by the inner ring. The stripper ring applies pressure to the material to be processed and also pushes solid material from between the upper and lower flanges to fall into a receiver for the solids.Type: GrantFiled: June 17, 2004Date of Patent: February 6, 2007Inventor: Gary Robertson
-
Publication number: 20070005489Abstract: Embodiments of the invention provide a method for selling integrated circuit manufacturing systems online, wherein the method includes receiving information representing a integrated circuit manufacturing system available for purchase, posting the information on an electronically viewable medium, and receiving an electronically transmitted bid for the integrated circuit manufacturing system from a buyer. The method further includes transmitting the bid to a seller, receiving a bid acceptance from the seller, and providing technical services related to the integrated circuit manufacturing system available for purchase to at least one of the buyer and seller through an integrated online service.Type: ApplicationFiled: September 5, 2006Publication date: January 4, 2007Inventors: KOICHI USUI, Tsutomu Tanaka, Masanori Takahashi, Kabita Das, Scott Ritterbush, Kumar Ramachandran, Gary Robertson
-
Patent number: 6877724Abstract: A zero emmission device and method for delivering constant concentration of a vaporized substance allows for the regulated use of chemical or biological substances, such as calibrating, exposure or therapeutic substances.Type: GrantFiled: March 31, 2003Date of Patent: April 12, 2005Assignee: The United States of America as represented by the Secretary of the NavyInventors: Jimmie D. Petty, Walter L. Cranor, James N. Huckins, David A. Alvarez, Gary Robertson
-
Publication number: 20040250839Abstract: An apparatus and method for the improved combined edge bead removal and backside wash of spin coated semiconductor wafers is disclosed. This is preferably accomplished by providing a nozzle having a plurality of outlets adapted for the ejection of a cleaning fluid onto the backside of a semiconductor wafer. This cleaning fluid can be EEP or a similar EBR type of solvent. This dual outlet nozzle can be mounted to a stationary EBR arm, and preferably comprises two outlets located on a beveled top surface that are separated at a predetermined angle. The angle of this beveled top surface with respect to a horizontal plane of the processed wafer is preferably about 45 degrees, while the angle of each nozzle outlet with respect to a primary axis of the stationary EBR arm is also preferably about 45 degrees. Other angles are also possible in order to maximize solvent jet efficiency.Type: ApplicationFiled: June 12, 2003Publication date: December 16, 2004Applicant: National Semiconductor CorporationInventors: Gary Robertson, Robert Boyd Finlay
-
Patent number: 6627860Abstract: A heat sensing device manager system and method for processing signals from heat sensing devices used to monitor the semiconductor processing environment. The system includes a circuit for determining if a heat sensing device has failed. Where a heat sensing device has failed the system can switch control of the system such that it relies on signals generated by operational heat sensing devices. The system also provides the user with an intuitive LED interface that provides the user with information regarding the operation of the heat sensing elements of the system, and where a heat sensing device has failed the user interface can convey information regarding the nature of a particular heat sensing device failure.Type: GrantFiled: November 8, 2001Date of Patent: September 30, 2003Inventor: Gary Robertson
-
Publication number: 20030028471Abstract: Embodiments of the invention provide a method for selling integrated circuit manufacturing systems online, wherein the method includes receiving information representing a integrated circuit manufacturing system available for purchase, posting the information on an electronically viewable medium, and receiving an electronically transmitted bid for the integrated circuit manufacturing system from a buyer. The method further includes transmitting the bid to a seller, receiving a bid acceptance from the seller, and providing technical services related to the integrated circuit manufacturing system available for purchase to at least one of the buyer and seller through an integrated online service.Type: ApplicationFiled: August 1, 2001Publication date: February 6, 2003Inventors: Koichi Usui, Tsutomu Tanaka, Masanori Takahashi, Kabita Das, Scott Ritterbush, Kumar Ramachandran, Gary Robertson
-
Patent number: 6231931Abstract: A method of coating a wooden substrate or surface comprising the steps of depositing a layer of ultraviolet light curable polymer in an uncured form to at least one surface of a wooden substrate; and curing said polymer with an amount of UV energy sufficient to polymerize said polymer. The method optionally comprising the further steps of: scuffing the surface of the cured polymer; depositing a second layer of ultraviolet light curable polymer in an uncured form to the scuffed surface; and curing the second layer of ultraviolet light curable polymer with an amount of UV energy sufficient to polymerize said second layer. The method also contemplates a further step comprising scuffing the surface of the cured polymer; and depositing a top coat thereon.Type: GrantFiled: March 2, 1999Date of Patent: May 15, 2001Inventors: John S. Blazey, Gary Robertson, Joseph C. Sgro
-
Patent number: 5407367Abstract: A dual level terminal assembly for use in connecting closely packed leads to a circuit board. The assembly includes an elongated base support and a lower barrier terminal strip mounted on a from portion of the support, and an upper barrier terminal strip mounted on a rear portion of the support which faces the from portion and which is at a higher level that the front portion.Type: GrantFiled: September 27, 1993Date of Patent: April 18, 1995Assignee: Vernitron CorporationInventor: Gary Robertson
-
Patent number: D331224Type: GrantFiled: May 9, 1991Date of Patent: November 24, 1992Assignee: Vernitron CorporationInventor: Gary Robertson