Abstract: A method includes determining whether transformer phases should be permuted. The method includes, responsive to a determination that the transformer phases should be permuted, permuting the transformer phases, based on historical aging information of transformer input phases, to cause transformer input phases with higher ages to be connected to transformer output phases with lower output loads and transformer input phases with lower ages to be connected to transformer output phases with higher output loads. Multiple apparatus and program products are also disclosed.

Abstract: A method includes determining whether transformer phases should be permuted. The method includes, responsive to a determination that the transformer phases should be permuted, permuting the transformer phases, based on historical aging information of transformer input phases, to cause transformer input phases with higher ages to be connected to transformer output phases with lower output loads and transformer input phases with lower ages to be connected to transformer output phases with higher output loads. Multiple apparatus and program products are also disclosed.

Abstract: A method, system and apparatus for operating an energy-using device are disclosed. Current data related to operation of the energy-using device is received at a remote device. An operating specification for the energy-using device is received at the remote device from a database. A recommended setting of the energy-using device is determined from the current data and the operating specification. The remote device communicates the recommended setting to the energy-using device. A control unit at the energy-using device receives the recommended setting and implements the recommended setting at the energy-using device.

Abstract: A method, system and apparatus for operating an energy-using device are disclosed. Current data related to operation of the energy-using device is received at a remote device. An operating specification for the energy-using device is received at the remote device from a database. A recommended setting of the energy-using device is determined from the current data and the operating specification. The remote device communicates the recommended setting to the energy-using device. A control unit at the energy-using device receives the recommended setting and implements the recommended setting at the energy-using device.

Abstract: A method includes determining whether transformer phases should be permuted. The method includes, responsive to a determination that the transformer phases should be permuted, permuting the transformer phases, based on historical aging information of transformer input phases, to cause transformer input phases with higher ages to be connected to transformer output phases with lower output loads and transformer input phases with lower ages to be connected to transformer output phases with higher output loads. Multiple apparatus and program products are also disclosed.

Abstract: A method, system and apparatus for operating an energy-using device are disclosed. Current data related to operation of the energy-using device is received at a remote device. An operating specification for the energy-using device is received at the remote device from a database. A recommended setting of the energy-using device is determined from the current data and the operating specification. The remote device communicates the recommended setting to the energy-using device. A control unit at the energy-using device receives the recommended setting and implements the recommended setting at the energy-using device.

Abstract: A method, system and apparatus for operating an energy-using device are disclosed. Current data related to operation of the energy-using device is received at a remote device. An operating specification for the energy-using device is received at the remote device from a database. A recommended setting of the energy-using device is determined from the current data and the operating specification. The remote device communicates the recommended setting to the energy-using device. A control unit at the energy-using device receives the recommended setting and implements the recommended setting at the energy-using device.

Abstract: Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element.

Abstract: A memory device for performing logical operations on two or more input variables includes a match line and first and second memory cells. The first and second memory cells collectively include a first, second, third and fourth memory element. The first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed.

Abstract: A memory device for storing one or more addresses includes a match line and first and second memory cells that form a 2-bit memory cell. Each memory cell includes two memory elements coupled to a match line and selection lines coupled thereto. The selection lines provide a signal representative of a logical combination of at least two different inputs.

Abstract: Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element.

Abstract: A memory system includes a content addressable memory (CAM) including a plurality of match lines, each match line having a plurality of memory cells coupled thereto. The system also includes a match detector coupled to the CAM and a reference match line having a plurality of reference memory cells coupled thereto, the reference memory cells being of the same type and the memory cells. The system also includes a match line sensor coupled to the reference match line and the match detector that determines a characteristic of the reference match line and provides a timing signal to the match detector based on the characteristic.

Abstract: A memory system for storing one or more addresses includes a transposable memory having word lines, bit lines, transposed word lines and transposed bit lines and that receives and stores an input array having dimensions M by N and a content addressable memory (CAM) that reads the transposed word lines of the transposable memory to form input words and that stores the input words in an N by M array.

Abstract: A memory system includes a content addressable memory (CAM) including a plurality of match lines, each match line having a plurality of memory cells coupled thereto. The system also includes a match detector coupled to the CAM and a reference match line having a plurality of reference memory cells coupled thereto, the reference memory cells being of the same type and the memory cells. The system also includes a match line sensor coupled to the reference match line and the match detector that determines a characteristic of the reference match line and provides a timing signal to the match detector based on the characteristic.

Abstract: A memory device for performing logical operations on two or more input variables includes a match line and first and second memory cells. The first and second memory cells collectively include a first, second, third and fourth memory element. The first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed.

Abstract: A method for generating a dual rate clock circuit the method including coupling the output terminal of a first local clock buffer to the input of a second local clock buffer through at least one inverter circuit and driving the first local clock buffer with a base signal. The method also includes generating an early clock signal with the first local clock buffer based on the base signal and generating a delayed early clock signal by delaying the first local clock signal with the at least one inverter. The method also includes generating a later clock signal by driving the second local clock buffer with the delayed early clock signal wherein the second local clock buffer and the late clock signal generated by the second local clock buffer are synchronized and correlated with the first local clock buffer and the early clock signal generated by the first local clock buffer.

Abstract: A circuit incorporating a current starved ring oscillator is coupled to a power gate switch in an integrated circuit. The circuit incorporating the current starved ring oscillator amplifies a voltage difference between a virtual ground associated with the power gate switch and ground, and converts the difference to a frequency. Digital logic monitors the output of the ring oscillator using a counter and a reference clock. Control circuitry controls operation of the integrated circuit in dependence on the monitored conditions associated with the power gate switch. A method monitors a virtual ground voltage across a power gate switch in an integrated circuit; and controls operation of the integrated circuit in dependence on the monitored virtual ground voltage.

Abstract: A circuit incorporating a current starved ring oscillator is coupled to a power gate switch in an integrated circuit. The circuit incorporating the current starved ring oscillator amplifies a voltage difference between a virtual ground associated with the power gate switch and ground, and converts the difference to a frequency. Digital logic monitors the output of the ring oscillator using a counter and a reference clock. Control circuitry controls operation of the integrated circuit in dependence on the monitored conditions associated with the power gate switch. A method monitors a virtual ground voltage across a power gate switch in an integrated circuit; and controls operation of the integrated circuit in dependence on the monitored virtual ground voltage.

Abstract: A circuit design method, computer program product and chip design system embodying the method. A gate selected for static timing analysis (STA) from a circuit design. Initial performance characteristics (e.g., load and transition slew) are determined for the selected gate. A charge equivalent effective capacitance (CQeff) is determined for the gate from the initial performance characteristics. A gate delay is determined in a single pass for the gate using CQeff as an effective load for said selected gate. Optionally, if the total gate load capacitance (Ctot) exceeds CQeff by less than a minimum, the effective capacitance (Ceff) is determined and used for determining the gate delay instead.

Abstract: Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of desired number of logical blocks and repeats the process of identifying logical blocks for different hierarchical levels of the integrated circuit design until the number of logical blocks is within the range of the desired number of logical blocks. This serves as a guide to partition the chip as opposed to a grid-like partitioning.