Abstract: A phase locked loop that operates on an input signal received from a disk drive and similar data processing system peripherals, where the input signal has a preamble portion and a data portion. The phase locked loop providing a digital clock signal which is phase locked to the preamble portion. This is accomplished by adjusting the loop response time so that it monotonically decreases in amplitude beginning at a time when the phase locked loop receives the preamble portion and continuing to monotonically decrease during at least a portion of the time that the phase locked loop receives the data portion. The response time may be monotonically decreased in any suitable fashion, such as linearly or exponentially. A specific embodiment of a linearly decreasing signal generator used with a charge pump is disclosed. The results of computer simulations showing a decrease in lock acquisition time and increased noise immunity with shortened preamble time are also discussed.