Patents by Inventor Gary S. Koch

Gary S. Koch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11957345
    Abstract: A cover for an articulation joint that is supported in an elongate shaft assembly of a surgical instrument that is operably coupled to a surgical end effector that includes at least one end effector conductor therein. The cover includes at least one electrically conductive pathway that extends from the distal end of the cover to form an electrically conductive pathway from the end effector conductor to a shaft conductor on the elongate shaft assembly while facilitating operation of the articulation joint. Various conductor arrangements facilitating the passage of electrical current between an end effector to a control system across the articulation joint are also disclosed.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: April 16, 2024
    Assignee: Cilag GmbH International
    Inventors: Gary S. Jaworek, Robert L. Koch, Jr., Michael D. Auld
  • Patent number: 6907554
    Abstract: A built-in self test system (124) and method for two-dimensional memory redundancy allocation. The built-in self test system is adapted to allocate two redundant columns (116) and one redundant row (120) to an embedded memory (104) as needed to repair single cell failures (SCFs) within the rows (108) and columns of the memory. The self-test system includes a left-priority encoder (136), a right-priority encoder (140), and a greater-than-two detector (144). The left-priority encoder encodes the location of the first SCF most proximate the most-significant bit of the corresponding word. The right-priority encoder encodes the location of the first SCF most proximate the least-significant bit of the corresponding word. The greater-than-two detector determines whether a word contains more than two SCFs.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: June 14, 2005
    Assignee: International Business Machines Corporation
    Inventors: R. Dean Adams, Thomas J. Eckenrode, Steven L. Gregor, Gary S. Koch
  • Publication number: 20040225939
    Abstract: A built-in self test system (124) and method for two-dimensional memory redundancy allocation. The built-in self test system is adapted to allocate two redundant columns (116) and one redundant row (120) to an embedded memory (104) as needed to repair single cell failures (SCFs) within the rows (108) and columns of the memory. The self-test system includes a left-priority encoder (136), a right-priority encoder (140), and a greater-than-two detector (144). The left-priority encoder encodes the location of the first SCF most proximate the most-significant bit of the corresponding word. The right-priority encoder encodes the location of the first SCF most proximate the least-significant bit of the corresponding word. The greater-than-two detector determines whether a word contains more than two SCFs.
    Type: Application
    Filed: May 9, 2003
    Publication date: November 11, 2004
    Applicant: International Business Machines Corporation
    Inventors: R. Dean Adams, Thomas J. Eckenrode, Steven L. Gregor, Gary S. Koch
  • Patent number: 6791855
    Abstract: The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: September 14, 2004
    Assignee: International Business Machines Corporation
    Inventors: Kevin A. Batson, Robert E. Busch, Gary S. Koch, Fred J. Towler, Reid A. Wistort
  • Patent number: 6728123
    Abstract: The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.
    Type: Grant
    Filed: April 15, 2002
    Date of Patent: April 27, 2004
    Assignee: International Business Machines Corporation
    Inventors: Kevin A. Batson, Robert E. Busch, Gary S. Koch, Fred J. Towler, Reid A. Wistort
  • Publication number: 20040052134
    Abstract: The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.
    Type: Application
    Filed: August 14, 2003
    Publication date: March 18, 2004
    Inventors: Kevin A. Batson, Robert E. Busch, Gary S. Koch, Fred J. Towler, Reid A. Wistort
  • Patent number: 6687144
    Abstract: A high-reliability content & addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: February 3, 2004
    Assignee: International Business Machines Corporation
    Inventors: Kevin A. Batson, Geordie M Braceras, Robert E. Busch, Gary S. Koch
  • Patent number: 6650561
    Abstract: A high-reliability content-addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: November 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: Kevin A. Batson, Geordie M. Braceras, Robert E. Busch, Gary S. Koch
  • Publication number: 20030202371
    Abstract: The present invention uses a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The invention may be used with or without priority encoders.
    Type: Application
    Filed: May 6, 2003
    Publication date: October 30, 2003
    Inventors: Kevin A. Batson, Geordie M. Braceras, Robert E. Busch, Gary S. Koch
  • Publication number: 20030193822
    Abstract: The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.
    Type: Application
    Filed: April 15, 2002
    Publication date: October 16, 2003
    Applicant: International Business Machines Corporation
    Inventors: Kevin A. Batson, Robert E. Busch, Gary S. Koch, Fred J. Towler, Reid A. Wistort
  • Publication number: 20030142525
    Abstract: The present invention uses a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The invention may be used with or without priority encoders.
    Type: Application
    Filed: January 30, 2002
    Publication date: July 31, 2003
    Applicant: International Business Machines Corporation
    Inventors: Kevin A. Batson, Geordie M. Braceras, Robert E. Busch, Gary S. Koch