Abstract: A “pinout mode” control capability incorporated into an integrated circuit device controls an internal mapping function, with the effect that the device pinout is adjusted by the setting of the pinout mode. An integrated circuit device includes a data interface with plural physical ports each having a physical port identifier and a mapper for mapping the physical port identifiers to logical port identifiers based on a selected mode setting, each mode setting defining a different port mapping. A data circuit is coupled to the data interface, the data circuit processing data sent to and received from the data interface based on the logical port identifiers.

Abstract: A multi-port line card redundancy technique automatically reconfigures ports on line cards of an intermediate network node, such as an aggregation router, in the event of a failure to one of the ports. The technique includes a circuit that automatically enables one of a pair of line cards to assume responsibility for transmission and reception of data in the event of a failure to one of the ports of a line card. Each line card is preferably a multi-port line card having a plurality of ports. The line cards are preferably further organized and arranged into redundant pairs. The redundancy technique is preferably directed to “1+1” redundancy wherein an external device, such as an end station, transmits identical data over two connections to the redundant line cards of the router.

Abstract: In one embodiment, an intermediate node includes one or more active forwarding planes and one or more redundant forwarding planes. The intermediate node may also include one or more active control planes and one or more redundant control planes. A test packet is generated, in some cases by a redundant control plane, and transferred to a redundant forwarding plane. The operational state of the redundant forwarding plane is verified, at least in part, by using operational software and hardware contained in the redundant forwarding plane to forward the test packet from the redundant forwarding plane to a target line card. The target line card loops the test packet back to the redundant forwarding plane as part of the verification process. In some cases, the redundant control plane processes the looped-back test packet.

Abstract: An aggregation router architecture comprises a plurality of line cards coupled to at least one performance routing engine (PRE) via an interconnect system. The line cards include input cards having input ports coupled to subscribers and at least one trunk card configured to aggregate packets received from the subscriber inputs over at least one output port. The PRE performs packet forwarding and routing operations, along with quality of service functions for the packets received from each input line card over the interconnect system. The interconnect system comprises a plurality of high-speed unidirectional (i.e., point-to-point) links coupling the PRE to each line card. The point-to-point links couple the line cards to a novel logic circuit of the PRE that is configured to interface the line cards to a packet buffer and a forwarding engine of the PRE.

Abstract: A flow bit mechanism and technique conveys per-channel flow control information pertaining to the status of output buffers located on line cards to at least one performance routing engine (PRE) of an intermediate network node, such as an aggregation router. Each line card generates a flow bit for each of its output buffers associated with an output channel. The state of the flow bit denotes a threshold reading on the depth of the output buffer, which is preferably organized as a first-in, first-out (FIFO) queue. The depth of the output queue is compared with a predetermined threshold value. If the depth of the FIFO is below the threshold, the state of the flow bit returned to the PRE indicates that more traffic can be accepted for that channel. If the depth of the FIFO is above the threshold, the state of the flow bit indicates that further traffic is denied for the channel until there is more space on the queue.

Abstract: An apparatus and technique configures an intermediate network node, such as an aggregation router, to implement automatic protection switching (APS) redundancy among its line cards in the event of a failure to one of those cards. The APS line card redundancy provides redundancy among a pair of line cards connected to a performance routing engine of the router. Internal APS data paths are implemented in the router through the provision of an alias logic circuit that selects packet data from one of an adjacent pair of line cards and sends identical copies of data to that adjacent pair of line cards.

Abstract: A bound mode mechanism and technique efficiently accommodates high-bandwidth data traffic flow within an intermediate node of a computer network. The bound mode mechanism combines two half-slot line card connectors of a backplane in an aggregation router into a single full-slot line card arrangement to thereby increase the bandwidth provided to a high-speed, full-height line card of the router. The technique is also capable of accommodating generic half-slot (i.e., subslot) connectors, each of which is capable of supporting a variety of data formats. The bound mode mechanism further allows use of a high-speed trunk card without the penalty of supporting high trunk level bandwidth on all of the slot connectors of the router. The mechanism enables use of a simple backplane, while also maintaining a low pin count on a backplane logic circuit of the router.

Abstract: An interconnect protocol enables encoding of packets for transmission over an interconnect system used to couple a plurality of line cards to at least one performance routing engine of an aggregation router. The protocol manifests as a unique encoding and encapsulation technique for data transmitted over point-to-point links of the interconnect system. The encapsulation technique includes an interconnect header which is attached to each packet. Framer logic is provided at a transmitter of the system to generate encoded frames from a stream of packet data for transmission over the links and at a receiver to recover the transmitted data from the frames.

Abstract: A technique for verifying an intermediate node that employs a forwarding plane and optionally a control plane. A test packet is generated and transferred to the forwarding plane. Using operational software and hardware, the forwarding plane forwards the test packet to a line card, which in turn “loops” the test packet back to the forwarding plane. Using operational software and hardware, the forwarding plane processes the looped-back test packet including forwarding the packet to a destination, such as a control plane, where the looped-back test packet is verified.

Abstract: A device and method for network communications and diagnostics are provided. One embodiment of the device includes a processor for generating a time-domain reflectometry testing stimulus signal when the device is operating in a network diagnostic mode. The testing signal is supplied to the network to cause the network to generate a reflection signal thereof from which presence and characteristics of a fault condition in the network may be determined.

Abstract: A field extraction system quickly extracts information from arbitrary fields of a data packet transferred among entities of a computer network. The system includes a field extractor having synchronously operated hardware circuitry that is programmable to extract the contents of a field from the packet and then to interpret these extracted contents. The programmable hardware-based field extraction system extracts the contents of a field within a fixed amount of time while also providing the flexibility needed to adapt to changing header standards so that information can be extracted from arbitrary fields of, e.g., a header of the packet.

Abstract: A network node destination module for ensuring proper reception and transmission of information over a network having an optional network reference clock including an input stage for receiving the information, a synchronous residual time stamp (SRTS) timing control stage for implementing digital phase comparison techniques utilizing the network reference clock, and a clock generation stage for generating a transmit clock in response to a control value generated by the SRTS timing control stage. The SRTS timing control stage maintains a constant phase offset between the receive clock of the source node and the transmit clock of the destination node. The SRTS timing control stage includes an RTS sample generator for generating a local RTS sample for comparison with the source RTS sample to determine a current phase offset between the source and clocks. The current phase offset is then compared to a target phase offset stored in a phase register to generate a control value.

Abstract: A network node destination module for ensuring proper reception and transmission of information over a network having an optional network reference clock including an input stage for receiving the information, a synchronous residual time stamp (SRTS) timing control stage for implementing digital phase comparison techniques utilizing the network reference clock, and a clock generation stage for generating a transmit clock in response to a control value generated by the SRTS timing control stage. The SRTS timing control stage maintains a constant phase offset between the receive clock of the source node and the transmit clock of the destination node. The SRTS timing control stage includes an RTS sample generator for generating a local RTS sample for comparison with the source RTS sample to determine a current phase offset between the source and clocks. The current phase offset is then compared to a target phase offset stored in a phase register to generate a control value.

Abstract: An improved SRTS clock recovery system of a network node comprising a novel adaptifier arrangement that continually monitors the flow of data through a data FIFO and briefly assumes control over the SRTS clock recovery system to permanently adjust the phase and/or temporarily adjust the frequency of a transmit clock to avoid dataflow errors. Specifically, the adaptifier includes a phase controller that permanently adjusts a target phase offset utilized by the SRTS clock recovery system to effect a permanent change in the transmit clock phase. A frequency controller of the adaptifier temporarily overrides an error signal generated by the SRTS clock recovery system prior to it being utilized by a clock generator to effect a temporary adjustment of the transmit clock frequency. Clock perturbations are minimized, including graceful entry and exit of adaptifier action. The adaptifier implements either or both adjustments to avoid an impending dataflow error based upon a number of predetermined conditions.

Abstract: An improved SRTS clock recovery system of a network node that adjusts the range of a received source RTS sample and a locally generated destination RTS sample to compensate for inherent characteristics of a network system. In addition, the improved system extends the range of the RTS samples to properly interpret large phase differences between a source node clock and transmit clock generated by the network node. This novel technique for interpreting source and destination RTS samples enables the improved network node to accurately recover a source clock frequency from a network transmission in a highly stressed network system. Specifically, the SRTS clock recovery system includes an RTS sample interpreter having a slope determinator for determining the expected average change in source and destination RTS samples over time.