Patents by Inventor Gary Steven Parnes

Gary Steven Parnes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power converter with dual ring network control
    Patent number: 8120935
    Abstract: A method for providing electric power to a power system includes receiving, at a slave node of a power converter having a plurality of slave nodes, a first synchronization signal via a first communication channel, the first synchronization signal purporting to represent a master timing characteristic of a master control node of the converter; receiving, at the slave node of the converter, a second synchronization signal via a second communication channel, the second synchronization signal purporting to represent a master timing characteristic of the master control node of the converter; synchronizing an internal timing characteristic of the slave control node with the master timing characteristic of the master control node using the first synchronization signal; determining that the first synchronization signal is invalid; and synchronizing an internal timing characteristic of the slave control node with the master timing characteristic of the master control node using the second synchronization signal.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: February 21, 2012
    Assignee: American Superconductor Corporation
    Inventors: Patrick S. Flannery, David G. Oteman, Matthew W. Tilstra, Gary Steven Parnes
  • POWER CONVERTER WITH DUAL RING NETWORK CONTROL
    Publication number: 20110267854
    Abstract: A method for providing electric power to a power system includes receiving, at a slave node of a power converter having a plurality of slave nodes, a first synchronization signal via a first communication channel, the first synchronization signal purporting to represent a master timing characteristic of a master control node of the converter; receiving, at the slave node of the converter, a second synchronization signal via a second communication channel, the second synchronization signal purporting to represent a master timing characteristic of the master control node of the converter; synchronizing an internal timing characteristic of the slave control node with the master timing characteristic of the master control node using the first synchronization signal; determining that the first synchronization signal is invalid; and synchronizing an internal timing characteristic of the slave control node with the master timing characteristic of the master control node using the second synchronization signal.
    Type: Application
    Filed: March 29, 2011
    Publication date: November 3, 2011
    Applicant: American Superconductor Corporation
    Inventors: Patrick S. Flannery, David G. Oteman, Matthew W. Tilstra, Gary Steven Parnes