Patents by Inventor Gary V. Fay

Gary V. Fay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5237183
    Abstract: The reverse breakdown voltage of a conventional insulated gate transistor is greatly increased by the addition of a lightly doped layer between the substrate and a buffer layer of the insulated gate transistor. The addition of the lightly doped layer does not increase the on resistance of the device, nor the cut-off time of the device. The lightly doped layer can be provided as an epitaxial layer along with the other epitaxial layers of the insulated gate transistor.
    Type: Grant
    Filed: December 14, 1989
    Date of Patent: August 17, 1993
    Assignee: Motorola, Inc.
    Inventors: Gary V. Fay, Bernard W. Boland
  • Patent number: 5100821
    Abstract: An improved semiconductor AC switch is described having internal bias generation for the power MOSFET switches and isolated control input. Dual power MOSFETS with substrate diodes are connected in series between source and load. DC gate bias for the MOSFETS is derived from an internal power supply containing energy storage which charges from the line, typically every half cycle. The gates of the power MOSFETS are tied to the internal bias generator through a voltage divider network containing a variable resistance controlled by an optical input signal. The internal energy storage may be a capacitor or solid state battery, preferably a monolithic thick or thin film battery. No transformers or external control bias generators are required and the resulting switch is particularly simple and compact.
    Type: Grant
    Filed: December 24, 1990
    Date of Patent: March 31, 1992
    Assignee: Motorola, Inc.
    Inventor: Gary V. Fay
  • Patent number: 5100829
    Abstract: MOSFET devices or circuits incorporating an improved substrate temperature sensing element are obtained by forming a PN junction directly on a thin (gate) dielectric region. The temperature sense junction is desirably formed in a poly layer. By mounting it directly on thin (gate) dielectric its thermal response to temperature changes in the substrate is improved while still being electrically isolated from the substrate. It is desirable to provide over-voltage protection elements coupled to the junction to avoid rupture of the underlying thin dielectric. Because the sense diode and all the over-voltage protection devices may be made of poly with junctions perpendicular to the substrate, the structure is particularly compact and simple to fabricate.
    Type: Grant
    Filed: March 1, 1991
    Date of Patent: March 31, 1992
    Assignee: Motorola, Inc.
    Inventors: Gary V. Fay, Stephen P. Robb, Judith L. Sutor, Lewis E. Terry
  • Patent number: 5025298
    Abstract: MOSFET devices or circuits incorporating an improved substrate temperature sensing element are obtained by forming a PN junction directly on a thin (gate) dielectric region. The temperature sense junction is desirably formed in a poly layer. By mounting it directly on thin (gate) dielectric its thermal response to temperature changes in the substrate is improved while still being electrically isolated from the substrate. It is desirable to provide over-voltage protection elements coupled to the junction to avoid rupture of the underlying thin dielectric. Because the sense diode and all the over-voltage protection devices may be made of poly with junctions perpendicular to the substrate, the structure is particularly compact and simple to fabricate.
    Type: Grant
    Filed: August 22, 1989
    Date of Patent: June 18, 1991
    Assignee: Motorola, Inc.
    Inventors: Gary V. Fay, Stephen P. Robb, Judith L. Sutor, Lewis E. Terry
  • Patent number: 5006737
    Abstract: An improved semiconductor AC switch is described having internal bias generation for the power MOSFET switches and isolated control input. Dual power MOSFETS with substrate diodes are connected in series between source and load. DC gate bias for the MOSFETS is derived from an internal power supply containing energy storage which charges from the line, typically every half cycle. The gates of the power MOSFETS are tied to the internal bias generator through a voltage divider network containing a variable resistance controlled by an optical input signal. The internal energy storage may be a capacitor or solid state battery, preferably a monolithic thick or thin film battery. No transformers or external control bias generators are required and the resulting switch is particularly simple and compact.
    Type: Grant
    Filed: April 24, 1989
    Date of Patent: April 9, 1991
    Assignee: Motorola Inc.
    Inventor: Gary V. Fay
  • Patent number: 4420700
    Abstract: A semiconductor current regulating and switching apparatus is described wherein an NMOS enhancement mode power transistor is used in the positive lead to regulate the flow of current from a power source to a load. In order to achieve a low resistance on-state for the NMOS power transistor, the control gate must be biased to a voltage which exceeds the positive voltage of the power source. This bias voltage is generated within the apparatus.
    Type: Grant
    Filed: May 26, 1981
    Date of Patent: December 13, 1983
    Assignee: Motorola Inc.
    Inventors: Gary V. Fay, Alvin Pshaenich