Abstract: A battery management system calculates expected run time for the information handling system from either an average or instantaneous power consumption and the remaining battery capacity. When power is attached to the battery, the battery management system compares an expected run time with a current usage day profile. If the information handling system is operating in a non-active use period or if system run time can extend sufficiently into the non-use period then a slow charge rate is applied which will charge the batteries up to a substantially charged state (e.g., 80-95% of full capacity) and top off of the battery is deferred such that battery is fully charged somewhat before the average beginning of the next day (e.g., approximately one to two hours before the average beginning of the next day).

Abstract: A battery management system calculates expected run time for the information handling system from either an average or instantaneous power consumption and the remaining battery capacity. When power is attached to the battery, the battery management system compares an expected run time with a current usage day profile. If the information handling system is operating in a non-active use period or if system run time can extend sufficiently into the non-use period then a slow charge rate is applied which will charge the batteries up to a substantially charged state (e.g., 80-95% of full capacity) and top off of the battery is deferred such that battery is fully charged somewhat before the average beginning of the next day (e.g., approximately one to two hours before the average beginning of the next day).

Abstract: A forced power down signal issues from an I/O device to an information handling system through an optical interconnect if the information handling system fails to power down in response to a normal power down message. A 100% duty cycle signal issues from an optical interface at the I/O device and is detected by an optical interface of the information handling system, which issues a command to force a power down of the information handling system in response to the forced power down signal.

Abstract: A forced power down signal issues from an I/O device to an information handling system through an optical interconnect if the information handling system fails to power down in response to a normal power down message. A 100% duty cycle signal issues from an optical interface at the I/O device and is detected by an optical interface of the information handling system, which issues a command to force a power down of the information handling system in response to the forced power down signal.

Abstract: A smart cart for automatically managing a plurality of information handling systems. The system provides a plurality of functions. For example, in certain embodiments, the system provides one or more of security authentication for distributing the notebooks, automatic asset tracking functionality; identification of notebook charge status; provides identification of asset information (e.g., an asset tag number, a serial number or a computer name); network access to push patch updates at night when units are not in use; and charging control to optimize system availability and prevent AC input circuit overload.

Abstract: A forced power down signal issues from an I/O device to an information handling system through an optical interconnect if the information handling system fails to power down in response to a normal power down message. A 100% duty cycle signal issues from an optical interface at the I/O device and is detected by an optical interface of the information handling system, which issues a command to force a power down of the information handling system in response to the forced power down signal.

Abstract: A forced power down signal issues from an I/O device to an information handling system through an optical interconnect if the information handling system fails to power down in response to a normal power down message. A 100% duty cycle signal issues from an optical interface at the I/O device and is detected by an optical interface of the information handling system, which issues a command to force a power down of the information handling system in response to the forced power down signal.

Abstract: A smart cart for automatically managing a plurality of information handling systems. The system provides a plurality of functions. For example, in certain embodiments, the system provides one or more of security authentication for distributing the notebooks, automatic asset tracking functionality; identification of notebook charge status; provides identification of asset information (e.g., an asset tag number, a serial number or a computer name); network access to push patch updates at night when units are not in use; and charging control to optimize system availability and prevent AC input circuit overload.

Abstract: Power management of an information handling system PCI Express bus dynamically adjusts the inactivity time at the bus that is determined before initiation of a low power state by analyzing the transitions between low power and operating states over time. Dwell times of the bus in the low power state are compared with an inactivity goal to determine if the inactivity time should be adjusted up, such as when the bus enters the low power state too often, or should be adjusted down, such as when the bus enters the low power state too infrequently. In one embodiment, the dwell time is the time from entry into a low power state until initiation of the transition to an operating state and the inactivity goal is the time required for the bus to enter and exit the low power state.

Abstract: Systems and methods are disclosed for managing cacheability of data blocks to improve processor power management. Data can be intelligently moved between cache memory and non-cache memory based upon expected processing needs. Alternatively, the data can remain in the same memory space, and the memory designation can be intelligently managed from a cache memory to non-cache memory designation and/or from non-cache memory to cache memory designation depending upon the expected processing needs. In addition, both data movement and memory space re-designation can be utilized in conjunction. By intelligently managing the cacheability of the memory space holding the data blocks, processing efficiency and power management efficiency can be improved, particularly for bus master devices and related circuitry.

Abstract: Power management of an information handling system PCI Express bus dynamically adjusts the inactivity time at the bus that is determined before initiation of a low power state by analyzing the transitions between low power and operating states over time. Dwell times of the bus in the low power state are compared with an inactivity goal to determine if the inactivity time should be adjusted up, such as when the bus enters the low power state too often, or should be adjusted down, such as when the bus enters the low power state too infrequently. In one embodiment, the dwell time is the time from entry into a low power state until initiation of the transition to an operating state and the inactivity goal is the time required for the bus to enter and exit the low power state.

Abstract: The impact of distributed capacitance on information handling system operations is reduced by introducing an impedance element in series with the ground of the source of the distributed capacitance for an overall reduction of capacitance. For instance, distributed capacitance is formed between a liquid crystal display illumination lamp and ground through a reflector disposed proximate the lamp and aligned so that an interior reflecting surface directs light toward imaging pixels. An insulating dielectric added to the outer surface of reflector and assembled to information handling system chassis ground with some surface area in common between the reflector and the system ground form a separate series capacitor between the lamp and ground. The insulation dielectric capacitance combines in series with the reflector capacitance to provide a resultant capacitance of less than the reflector capacitance.

Abstract: A method and system for reducing snoop traffic on a processor bus coupling a cache memory and a processor. The processor is unable to perform a snoop operation while operating in a lower power state to conserve power. A copy of cache tag is maintained in a memory controller coupled to the processor bus. The memory controller performs snoop operations on the copy of the cache tag while the processor is placed in the lower power state. The processor exits the lower power state when an access to a modified cached line occurs.

Abstract: The impact of distributed capacitance on information handling system operations is reduced by introducing an impedance element in series with the ground of the source of the distributed capacitance for an overall reduction of capacitance. For instance, distributed capacitance is formed between a liquid crystal display illumination lamp and ground through a reflector disposed proximate the lamp and aligned so that an interior reflecting surface directs light toward imaging pixels. An insulating dielectric added to the outer surface of reflector and assembled to information handling system chassis ground with some surface area in common between the reflector and the system ground form a separate series capacitor between the lamp and ground. The insulation dielectric capacitance combines in series with the reflector capacitance to provide a resultant capacitance of less than the reflector capacitance.

Abstract: The present disclosure describes a system, method and software for informing an information handling system user as to the effect or consequences of changing operational characteristics of an information handling system component. In particular, the present disclosure provides a method for communicating the effects of user preference settings in an information handling system. The method provides for the display of a component control for a selected component operable to effect a user preference setting concerning the selected component. The method also provides for the display of an operating status for a component related to the selected component, the operating status resulting from effecting the user preference setting on the selected component. As a result, when a user changes one or more operational aspects of a component, the user is presented with the consequences of such changes on the operating status of related system components.

Abstract: A system and method for managing power consumption and data integrity in a computer system is disclosed in which the a memory controller of the computer system records in a buffer the addresses of writes to system memory that occur during the period that the processor is in a low power state. When the processor exits the low power state, the processor invalidates in its internal cache those cache lines that correspond to the addresses recorded in the buffer.

Abstract: A method and system for reducing snoop traffic on a processor bus coupling a cache memory and a processor. The processor is unable to perform a snoop operation while operating in a lower power state to conserve power. A copy of cache tag is maintained in a memory controller coupled to the processor bus. The memory controller performs snoop operations on the copy of the cache tag while the processor is placed in the lower power state. The processor exits the lower power state when an access to a modified cached line occurs.

Abstract: An information handling system includes a microprocessor, a storage, a plurality of devices operatively connected to said microprocessor and a run voltage rail, a sleep regulator, and a power management controller. The plurality of devices are further operatively connected to a run voltage power rail to operate in a run mode in response to a run voltage Vrun applied to the run voltage power rail. The sleep regulator provides a sleep voltage Vsleep output. Lastly, the power management controller determines a power savings sleep voltage for a run/sleep mode power management condition and controls the sleep power voltage output of the sleep regulator according to the power savings sleep voltage. The power management controller is further configured to enable select ones of the plurality of devices to be operatively disconnected from the Vrun power rail and connected to the sleep voltage Vsleep output, wherein devices operatively connected to the sleep voltage Vsleep output operate in a sleep power mode.

Abstract: The described embodiments of the present invention provide a computer docking station having connection means for coupling to an external monitor and an external keyboard, means for connecting the portable computer to the docking station, and at least one PCMCIA option card slot in the docking station. In a preferred embodiment, the computer docking station further includes a controller in the docking station to provide the necessary hardware interface between the PCMCIA cart slot and the portable computer and software means for providing the necessary driver support.

Abstract: The described embodiments of the present invention provide a computer docking system and method for connecting a portable computer to a docking station and method for coupling the docking station to an external monitor and an external keyboard and a technique for customizing the hardware configuration in the docking station for optimum performance. In a preferred embodiment, the technique for customizing the program hardware in the docking station is capable of customizing common hardware in various docking stations.