Patents by Inventor Gary W. Elsesser

Gary W. Elsesser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170206068
    Abstract: An optimization system to apply directives to a computer program without having to perform repeated front-end compilations of source code of the computer program is provided. In some embodiments, the optimization system performs a first compilation of the source code of the program to generate first front-end code and first back-end code of the computer program. The compilation includes a first front-end compilation and a first back-end compilation. The optimization system identifies a compiler directive to apply to a location within the first front-end code. The optimization system then performs a second back-end compilation of the first front-end code factoring in the compiler directive to generate second back-end code affected by the compiler directive.
    Type: Application
    Filed: May 9, 2016
    Publication date: July 20, 2017
    Inventors: Brian H. Johnson, Heidi Poxon, Luiz DeRose, Gary W. Elsesser, Clayton D. Andreasen, John Levesque
  • Patent number: 9015656
    Abstract: A system implementing a method for generating code for execution based on a SIMT model with parallel units of threads is provided. The system identifies a loop within a program that includes vector processing. The system generates instructions for a thread that include an instruction to set a predicate based on whether the thread of a parallel unit corresponds to a vector element. The system also generates instructions to perform the vector processing via scalar operations predicated on the predicate. As a result, the system generates instructions to perform the vector processing but to avoid branch divergence within the parallel unit of threads that would be needed to check whether a thread corresponds to a vector element.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 21, 2015
    Assignee: Cray Inc.
    Inventors: Terry D. Greyzck, William R. Fulton, David W. Oehmke, Gary W. Elsesser
  • Patent number: 5765181
    Abstract: A system and address method for extracting a PE number and offset from an array index. According to one aspect of the present invention, a processing element number is assigned to each processing element, a local memory address is assigned to each memory location and a linearized index is assigned to each array element in an array. The processing element number of the processing element in which a particular array element is stored is computed as a function of a linearized index associated with the array element and a distribution specification associated with the array. In addition, a local memory address associated with the array element is computed as a function of the linearized index and the distribution specification.
    Type: Grant
    Filed: December 10, 1993
    Date of Patent: June 9, 1998
    Assignee: Cray Research, Inc.
    Inventors: Steven M. Oberlin, Janet M. Eberhart, Gary W. Elsesser, Eric C. Fromm, Thomas A. MacDonald, Douglas M. Pase, Randal S. Passint