Abstract: An improved computer system having DMA-like capabilities for transferring data between a memory device and a peripheral device. The system has a processor connected to an address bus and a data bus. A memory is also connected to the address bus and the data bus. A peripheral device is connected to the data bus. A decoder is connected to the address bus for decoding the address signal on the address bus generated by the processor. The decoder generates a first control signal in response to the address signal detected on the address bus. Transceivers or bus drivers are placed in the data bus which are responsive to the first control signal generated by the decoder. The transceivers permit data flow on the data bus directly between the peripheral device and the memory. By placing an address signal on the address bus such that the decoder would decode that address, the system causes the memory device to transfer data to or from the peripheral device.

Abstract: In the present invention a digital communication controller for interfacing with a master processor and a synchronous bus having a plurality of slave processors connected thereto is disclosed. The digital communication controller provides synchronous transfer of instruction and data in each microcycle to the bus. However, the data provided in each microcycle is multiplexed such that it is associated with the instruction transmitted previously but not contiguous in time therewith.