Abstract: A system and method of enhancing the mitigation of side channel attacks on platform interconnects using endpoint HW based detection, synchronization, and re-keying include generating a set of keys for link encryption based on a high entropy seed, storing the set of keys in a deterministic order in a register, detecting that a re-key programmable threshold is met during link encryption with a device, identifying a synchronization point associated with the device, where the synchronization point indicates the device is ready to switch a current key used for link encryption, and synchronizing a rekeying event with the device.

Abstract: The present disclosure is directed to enabling operation of a field programmable gate array (FPGA) while preventing application quiescence during FPGA reconfiguration. In embodiments of the disclosure, proxy agent firmware may enable downstream transactions (e.g., PCIe transactions) to be serviced during reconfiguration of the FPGA. Programmable logic states (e.g., PCIe configuration states or memory-mapped input/output (MMIO) states) are saved in memory and maintained by the proxy agent (via a management controller running the proxy agent). Once the FPGA is reconfigured, the state may be restored to the FPGA's programmable logic, and the FPGA may operate on the current state of the transactions.

Abstract: Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable coarse-grain routing network may be implemented on an active interposer die. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. A protocol-based network on chip (NoC) may be overlaid on the coarse-grain routing network. Although the NoC protocol is nondeterministic, the coarse-grain routing network includes an array of programmable switch boxes linked together using a predetermined number of routing channels to provide deterministic routing. Pipeline registers may be interposed within the routing channels at fixed locations to guarantee timing closure.

Abstract: Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable coarse-grain routing network may be implemented on an active interposer die. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. A protocol-based network on chip (NoC) may be overlaid on the coarse-grain routing network. Although the NoC protocol is nondeterministic, the coarse-grain routing network includes an array of programmable switch boxes linked together using a predetermined number of routing channels to provide deterministic routing. Pipeline registers may be interposed within the routing channels at fixed locations to guarantee timing closure.

Abstract: Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable coarse-grain routing network may be implemented on an active interposer die. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. A protocol-based network on chip (NoC) may be overlaid on the coarse-grain routing network. Although the NoC protocol is nondeterministic, the coarse-grain routing network includes an array of programmable switch boxes linked together using a predetermined number of routing channels to provide deterministic routing. Pipeline registers may be interposed within the routing channels at fixed locations to guarantee timing closure.

Abstract: Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable coarse-grain routing network may be implemented on an active interposer die. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. A protocol-based network on chip (NoC) may be overlaid on the coarse-grain routing network. Although the NoC protocol is nondeterministic, the coarse-grain routing network includes an array of programmable switch boxes linked together using a predetermined number of routing channels to provide deterministic routing. Pipeline registers may be interposed within the routing channels at fixed locations to guarantee timing closure.

Abstract: A transceiver circuit includes a clock management circuit that generates control signals indicating power state information for logic circuits. The clock management circuit changes the power state information indicated by the control signals based on a change in an indication of a power state that is generated by an external source and that is received in a data stream at the transceiver circuit or based on a change in an amount of data stored in an internal queue. The transceiver circuit also includes a dynamic clock control circuit that receives the control signals and that generates a clock signal that is provided to the logic circuits. The dynamic clock control circuit adjusts a frequency of the clock signal based on the control signals indicating a change in the power state information generated by the clock management circuit to adjust the power state of the logic circuits.

Abstract: In one embodiment, transceiver circuitry includes a first-in-first-out (FIFO) circuit and a control logic circuit. The FIFO circuit receives data signals based on a first clock frequency and outputs stored data signals based on a second clock frequency. The stored data signals are transmitted out of the FIFO circuit only in response to a difference between a value of a write pointer of the FIFO circuit and a value of a read pointer of the FIFO circuit exceeding an empty threshold limit of the FIFO circuit. The control logic circuit may be utilized to adjust the empty threshold limit of the FIFO circuit.

Abstract: An integrated circuit includes programmable circuits, a configuration status register circuit, a mode register circuit, a mode decoder circuit, and a multiplexer circuit. The configuration status register circuit stores configuration bits and is coupled to provide the configuration bits to the programmable circuits to program the programmable circuits to implement functions of a first mode. The mode register circuit is coupled to store mode bits. The mode decoder circuit decodes at least a subset of the mode bits received from the mode register circuit to generate decoded bits. The multiplexer circuit is coupled to provide the decoded bits from the mode decoder circuit to the programmable circuits to reprogram the programmable circuits to implement functions of a second mode.

Abstract: An integrated circuit die includes interface and adapter circuits. The interface circuit exchanges data with an external device outside the integrated circuit die using a first clock signal. The interface circuit has a clock signal generation circuit to generate the first clock signal based on a second clock signal. The adapter circuit exchanges the data with the interface circuit. A frequency of the second clock signal is changed in response to an indication of a change in a data rate of the data. The adapter circuit causes the interface circuit to provide an adjustment to the first clock signal after the frequency of the second clock signal changes. The adapter circuit prevents the exchange of the data between the interface circuit and the external device until the adapter circuit receives an indication of completion of the adjustment to the first clock signal.

Abstract: An integrated circuit die includes interface and adapter circuits. The interface circuit exchanges data with an external device outside the integrated circuit die using a first clock signal. The interface circuit has a clock signal generation circuit to generate the first clock signal based on a second clock signal. The adapter circuit exchanges the data with the interface circuit. A frequency of the second clock signal is changed in response to an indication of a change in a data rate of the data. The adapter circuit causes the interface circuit to provide an adjustment to the first clock signal after the frequency of the second clock signal changes. The adapter circuit prevents the exchange of the data between the interface circuit and the external device until the adapter circuit receives an indication of completion of the adjustment to the first clock signal.